Abstract: A system is provided. The system may a memory device and a processor configured to: (1) receive user activity data from a plurality of venue systems associated with a plurality of different venues, the user activity data relating to user activity at gaming devices at the plurality of different venues; (2) identify the user activity as relating to a first user based on a linking between a stored value account associated with the first user and a plurality of loyalty accounts associated with the first user and with a corresponding one of the plurality of venue systems; (3) update global user activity records associated with the first user based on the received user activity data; and (4) transmit global user activity records associated with the first user to a first venue system of the plurality of venue systems that is associated with a first venue.

Abstract: A system is provided. The system may include a memory device and a processor configured to (1) determine a session has been established by a user at a gaming device associated with a CMS; (2) receive a transaction request associated with a gaming device, the transaction request identifying a transaction amount; (3) in response to determining the session has been established and receiving the transaction request, transmit instructions to cause an immutable CL to record a virtual transfer of funds record equal to the transaction amount from a virtual user account associated with the user to a venue virtual account; and (4) transmit instructions to a venue system to cause the CMS to initiate a transfer of the transaction amount from the venue gaming account to a credit balance of the gaming device.

Abstract: A system for location-aware authentication is configured to receive an authentication request associated with an identifier of a user for accessing an application and retrieves user information associated with the identifier and the application. The system then determines that the user information includes a geofence and information associated with a device of the user. Based on the geofence and the device information, the system sends a geolocation data request to the device, causing the device to gather and send the device's current geolocation data to the computing system. A data structure is generated to store data related to the device's current geolocation and sent to the application, which in turn causes the application to grant or deny the authentication request.

Abstract: Disclosed herein, are peptides capable of activating proteasome activity, and pharmaceutical compositions containing the peptides and methods treating Alzheimer's disease. Disclosed herein are compositions comprising: A) a peptide, wherein the peptide comprises the amino acid sequence GRKKR-RQ-AibG-RPS (SEQ ID NO: 4), or a fragment or variant thereof, B) a peptide, wherein the peptide comprises the amino acid sequence GRKKRRQ-AibG-QR-RKKRG (SEQ ID NO: 5), or a fragment or variant thereof, or C) a peptide, wherein the peptide comprises the amino acid sequence KKK/KKK-DABA-K KK (SEQ ID NO: 6) or a fragment or variant thereof.

Abstract: A system for location-aware authentication is configured to receive an authentication request associated with an identifier of a user for accessing an application and retrieves user information associated with the identifier and the application. The system then determines that the user information includes a geofence and information associated with a device of the user. Based on the geofence and the device information, the system sends a geolocation data request to the device, causing the device to gather and send the device's current geolocation data to the computing system. A data structure is generated to store data related to the device's current geolocation and sent to the application, which in turn causes the application to grant or deny the authentication request.

Abstract: There is provided a memory unit (100). The memory unit comprises a plurality of memory cells (110), each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b), a pre-charge circuit (150) configured to provide a voltage for charging the bit lines, and a multiplexer circuit. The multiplayer circuit (140) comprises, for each bit line, an associated NMOS (142a, 142b) device that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit (150) when activated by a corresponding bit line selection signal, and a multiplex controller (144) that is configured to be able to select each pair of bit lines by activating the associated NMOS devices (142a, 142b) using the corresponding bit lines selection signals.

Abstract: There is provided a memory unit (100). The memory unit comprises a plurality of memory cells (110), each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b), a pre-charge circuit (150) configured to provide a voltage for charging the bit lines, and a multiplexer circuit.

Abstract: There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line.

Abstract: The present invention provides a memory unit (4) comprising: a storage element (6) comprising a pair of back to back inverters (12a, 12b and 14a, 14b) having respective first and second storage access nodes (24, 26); first and second voltage lines (VSS, VDD 16a, 6b) across which said pair of back to back inverters (12a, 12b and 14a, 14b) are connected; a first access transistor (18a), connected to said first storage node (24); a second access transistor (18b), connected to said second storage node (26); a write word line (22) connected to a gate (18g1) on said first access transistor (18a) and a gate (18g2) on said second access transistor (18b); a first bit line (28) operably connected for controlling 10 said node (24); a second bit line (30) operably connected for controlling said node (26); in which there is provided a data dependent conductive path (46) between the first and second bit lines (28, 30).

Abstract: There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line.

Abstract: The present invention provides a memory unit (4) comprising: a storage element (6) comprising a pair of back to back inverters (12a, 12b and 14a, 14b) having respective first and second storage access nodes (24, 26); first and second voltage lines (VSS, VDD 16a, 6b) across which said pair of back to back inverters (12a, 12b and 14a, 14b) are connected; a first access transistor (18a), connected to said first storage node (24); a second access transistor (18b), connected to said second storage node (26); a write word line (22) connected to a gate (18g1) on said first access transistor (18a) and a gate (18g2) on said second access transistor (18b); a first bit line (28) operably connected for controlling 10 said node (24); a second bit line (30) operably connected for controlling said node (26); in which there is provided a data dependent conductive path (46) between the first and second bit lines (28, 30).

Abstract: The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90°. This feature is useful in clock/data recovery where the 90° “jumps” can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads.

Abstract: The present invention provides an apparatus and method of generating a set of 8 clock signals nominally spaced at equal 45° intervals by phase interpolation from a set of 4 quadrature reference clocks. The scheme is useful for clock generation for data capture in an oversampled clock/data recovery (CDR) system where the frequency of data sampling is twice that of the frequency of reference clock edges.

Abstract: Clock recovery apparatus having an early/late voter for deciding whether a current sampling point needs to be advanced or retarded, wherein the early/late voter passes and Up/Down signal to an interpolator for maintaining a clock signal; a frequency accumulator and rate multiplier 30 for generating further signals which are summed with those of the Up/Down signal of the early/late voter to provide an improved control signal to the phase interpolator. The accumulator is responsive to frequency changes in the input signal, and the interpolator acts on said Up/Down signals to adjust the clock signal by stepping it forward or backward according to control need, so that the sampling point can be advanced or retarded.

Abstract: A receiver equalizer with a first equalizer unit having a basic equalizer stage and a negative impedance cell connected to the basic equalizer stage. Preferably the negative impedance cell has a pair of back to back transistors, and connected thereto a parallel resistor capacitor RC network. The basic equalizer stage has a pair of current sources; a pair of transistors arranged as a differential pair, each transistor connected to a different one of the current sources; and a degeneration impedance connected in between the two current sources, and the transistors, wherein the negative impedance cell is connected across the outputs of the pair of transistors.

Abstract: There is provided a clock phase interpolator comprising a pair of output nodes, at least three complementary clock signal inputs, an equal plurality of current sources, and an equal plurality of clock switching sections. Each clock switching section is connected to switch, under the control of a complementary clock signal on a respective one of the complementary clock signal inputs, the current provided by a respective one of the current sources between the two output nodes. The current sources are controllable to provide interpolation between signals on the complementary clock signal inputs. Also provided is a clock phase interpolator comprising a pair of output nodes, two complementary clock signal inputs, an equal plurality of current sources, an equal plurality of clock switching sections.

Abstract: There is provided a method and apparatus for performing an eye scan. Said apparatus comprises: a receiver for receiving input signals; an equaliser for processing said input signals; a data sampler for sampling said processed input signals at certain sampling points to produce a data output, said data sampler being controlled by a clock signal; an edge sampler for detecting the edges of the processed input signal; an early/late voter for deciding whether a current sampling point needs to be advanced or retarded. The early/late voter passes an Up/Down signal to an interpolator for maintaining said clock signal, said interpolator acting on said Up/Down signal to adjust the clock signal by stepping it forward or backward according to control need, so that said sampling point can be advanced or retarded.

Abstract: A steering current generator for a phase interpolator has a multiplicity of fine phase adjustment current sources, each of which is switchable to direct its current to one or other of two summing nodes. The current of each of those two summing nodes is supplemented by respective fixed always-on current sources. The steering current generator has four current outputs and a switching matrix is provided to switch the current from the summing nodes to first and second selected ones of those outputs. The switching matrix is also connected to switch bleed currents to the other two of the current outputs.

Abstract: There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving node, first and second push-pull drive stages each having a current path connected between a second power supply, having a second potential, and the driving node, and each having a control input for one half of a CML signal and an output node. Each of the two output nodes is connected to the control node of a respective one of the current sources, each current source being connected to decrease the current it supplies to the driving node if the potential of its respective output of the converter moves towards the potential of the first power supply.

Abstract: A user information user interface for a networked software service is provided. The user information user interface corresponds to a request for information and is generated to overlap the software service user interface. The user information user interface includes a pointer to a display control on the software service user interface and data corresponding to the display control. The user information user interface can also include a set of selectable icons to facilitate selection of different display controls.