Patents by Inventor Andrew Putnam
Andrew Putnam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11593138Abstract: A physical server with an offload card including a SoC (system-on-chip) and a FPGA (field programmable gate array) is disclosed. According to one set of embodiments, the SoC can be configured to offload one or more hypervisor functions from a CPU complex of the server that are suited for execution in software, and the FPGA can be configured to offload one or more hypervisor functions from the CPU complex that are suited for execution in hardware.Type: GrantFiled: March 3, 2020Date of Patent: February 28, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Derek Chiou, Andrew Putnam, Daniel Firestone, Jack Lavier
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Patent number: 10949379Abstract: Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a method includes receiving, from a computing network, a packet at a packet processor of a server. The method also includes matching the received packet with a flow in a flow table contained in the packet processor and determining whether the action indicates that the received packet is to be forwarded to a NIC buffer in the outbound processing path of the packet processor instead of the NIC. The method further includes in response to determining that the action indicates that the received packet is to be forwarded to the NIC buffer, forwarding the received packet to the NIC buffer and processing the packet in the NIC buffer to forward the packet to the computer network without exposing the packet to the main processor.Type: GrantFiled: February 27, 2020Date of Patent: March 16, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Sambhrama Mundkur, Fengfen Liu, Norman Lam, Andrew Putnam, Somesh Chaturmohta, Daniel Firestone, Alec Kochevar-Cureton
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Publication number: 20200371828Abstract: A physical server with an offload card including a SoC (system-on-chip) and a FPGA (field programmable gate array) is disclosed. According to one set of embodiments, the SoC can be configured to offload one or more hypervisor functions from a CPU complex of the server that are suited for execution in software, and the FPGA can be configured to offload one or more hypervisor functions from the CPU complex that are suited for execution in hardware.Type: ApplicationFiled: March 3, 2020Publication date: November 26, 2020Inventors: Derek CHIOU, Andrew PUTNAM, Daniel FIRESTONE, Jack LAVIER
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Patent number: 10789199Abstract: Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a computing device includes a field programmable gate array (“FPGA”) that includes an inbound processing path and outbound processing path in opposite processing directions. The inbound processing path can forward a packet received from the computer network to a buffer on the FPGA instead of the NIC. The outbound processing path includes an outbound multiplexer having a rate limiter circuit that only forwards the received packet from the buffer back to the computer network when a virtual port corresponding to the packet has sufficient transmission allowance. The outbound multiplexer can also periodically increment the transmission allowance based on a target bandwidth for the virtual port.Type: GrantFiled: February 28, 2018Date of Patent: September 29, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Sambhrama Mundkur, Fengfen Liu, Norman Lam, Andrew Putnam, Somesh Chaturmohta, Daniel Firestone
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Publication number: 20200265005Abstract: Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a method includes receiving, from a computing network, a packet at a packet processor of a server. The method also includes matching the received packet with a flow in a flow table contained in the packet processor and determining whether the action indicates that the received packet is to be forwarded to a NIC buffer in the outbound processing path of the packet processor instead of the NIC. The method further includes in response to determining that the action indicates that the received packet is to be forwarded to the NIC buffer, forwarding the received packet to the NIC buffer and processing the packet in the NIC buffer to forward the packet to the computer network without exposing the packet to the main processor.Type: ApplicationFiled: February 27, 2020Publication date: August 20, 2020Inventors: Sambhrama Mundkur, Fengfen Liu, Norman Lam, Andrew Putnam, Somesh Chaturmohta, Daniel Firestone, Alec Kochevar-Cureton
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Patent number: 10614028Abstract: Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a method includes receiving, from a computing network, a packet at a packet processor of a server. The method also includes matching the received packet with a flow in a flow table contained in the packet processor and determining whether the action indicates that the received packet is to be forwarded to a NIC buffer in the outbound processing path of the packet processor instead of the NIC. The method further includes in response to determining that the action indicates that the received packet is to be forwarded to the NIC buffer, forwarding the received packet to the NIC buffer and processing the packet in the NIC buffer to forward the packet to the computer network without exposing the packet to the main processor.Type: GrantFiled: November 28, 2017Date of Patent: April 7, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Sambhrama Mundkur, Fengfen Liu, Norman Lam, Andrew Putnam, Somesh Chaturmohta, Daniel Firestone
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Patent number: 10332008Abstract: A decision tree multi-processor system includes a plurality of decision tree processors that access a common feature vector and execute one or more decision trees with respect to the common feature vector. A related method includes providing a common feature vector to a plurality of decision tree processors implemented within an on-chip decision tree scoring system, and executing, by the plurality of decision tree processors, a plurality off decision trees, by reference to the common feature vector. A related decision tree-walking system includes feature storage that stores a common feature vector and a plurality of decision tree processors that access the common feature vector from the feature storage and execute a plurality of decision trees by comparing threshold values of the decision trees to feature values within the common feature vector.Type: GrantFiled: March 17, 2014Date of Patent: June 25, 2019Assignee: Microsoft Technology Licensing, LLCInventors: Douglas C. Burger, James R. Larus, Andrew Putnam, Jan Gray
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Publication number: 20190081899Abstract: Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a computing device includes a field programmable gate array (“FPGA”) that includes an inbound processing path and outbound processing path in opposite processing directions. The inbound processing path can forward a packet received from the computer network to a buffer on the FPGA instead of the NIC. The outbound processing path includes an outbound multiplexer having a rate limiter circuit that only forwards the received packet from the buffer back to the computer network when a virtual port corresponding to the packet has sufficient transmission allowance. The outbound multiplexer can also periodically increment the transmission allowance based on a target bandwidth for the virtual port.Type: ApplicationFiled: February 28, 2018Publication date: March 14, 2019Inventors: Sambhrama Mundkur, Fengfen Liu, Norman Lam, Andrew Putnam, Somesh Chaturmohta, Daniel Firestone
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Publication number: 20190081891Abstract: Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a method includes receiving, from a computing network, a packet at a packet processor of a server. The method also includes matching the received packet with a flow in a flow table contained in the packet processor and determining whether the action indicates that the received packet is to be forwarded to a NIC buffer in the outbound processing path of the packet processor instead of the NIC. The method further includes in response to determining that the action indicates that the received packet is to be forwarded to the NIC buffer, forwarding the received packet to the NIC buffer and processing the packet in the NIC buffer to forward the packet to the computer network without exposing the packet to the main processor.Type: ApplicationFiled: November 28, 2017Publication date: March 14, 2019Inventors: Sambhrama Mundkur, Fengfen Liu, Norman Lam, Andrew Putnam, Somesh Chaturmohta, Daniel Firestone
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Publication number: 20150262062Abstract: Disclosed herein are systems and methods for coding decision trees, such as for execution on a decision tree scorer system. A computing system determines, for a particular feature of a plurality of features included in one or more decision trees, a list of unique threshold values associated with the particular feature in the one or more decision trees. The computing system determines a plurality of threshold index values for the list of unique threshold values, and represents the one or more decision trees such that decision nodes of the one or more decision trees associated with the particular feature include ones of the threshold index values.Type: ApplicationFiled: March 17, 2014Publication date: September 17, 2015Applicant: Microsoft CorporationInventors: Douglas C. Burger, James R. Larus, Andrew Putnam, Jan Gray
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Publication number: 20150262064Abstract: Disclosed herein is a decision tree multi-processor system. The system includes a plurality of decision tree processors that access a common feature vector and execute one or more decision trees with respect to the common feature vector.Type: ApplicationFiled: March 17, 2014Publication date: September 17, 2015Applicant: MICROSOFT CORPORATIONInventors: Douglas C. Burger, James R. Larus, Andrew Putnam, Jan Gray
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Publication number: 20150262063Abstract: Disclosed herein are systems, on-chip processors, and methods for executing decision trees. Decision tree circuitry retrieves a plurality of decision trees, which include feature locations and threshold values. A subset of the decision nodes includes next node data. The decision tree circuitry executes the decision nodes and determines next decision nodes to be retrieved and executed based on outcomes of the execution of the decision nodes. First outcomes of decision tree node executions result in determining the next decision nodes of the plurality of decision nodes based on the next node data. Second outcomes of the decision tree node executions result in determining the next decision nodes that are adjacent to currently executing nodes of the plurality of decision nodes.Type: ApplicationFiled: March 17, 2014Publication date: September 17, 2015Applicant: Microsoft CorporationInventors: Douglas C. Burger, James R. Larus, Andrew Putnam, Jan Gray
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Publication number: 20110143378Abstract: The present invention provides a disposable microfluidic assay cartridge (1) which will contain at least one sample inlet well (2) that will feed into a microfluidic sub-unit (3) embedded within the disposable microfluidic assay cartridge (1). The microfluidic sub-unit (3) contains a series of microfluidic channels and micro-valves (4) that direct the sample from the sample inlet well (2) to separate and fluidicly-isolated reaction vessels (5) that contain encoded or non-encoded beads microparticles (6) which have been functionalized with a capture moiety or capture molecules such as antibodies, antigens, or oligomers. Assay reagents (7) including reagents R1, R2, R3, R4, such as labeled antibodies, will be introduced into the separate and fluidicly-isolated reaction vessels (5) via the series of microfluidic channels (8) and micro-valves (4).Type: ApplicationFiled: November 12, 2010Publication date: June 16, 2011Applicant: CyVek LLC.Inventor: Martin Andrew PUTNAM
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Publication number: 20070271556Abstract: A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar.” WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i.e., a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks. Finally, a simple fence instruction is used to allow applications to handle relaxed memory consistency.Type: ApplicationFiled: July 30, 2007Publication date: November 22, 2007Applicant: University of WashingtonInventors: Susan Eggers, Martha Mercaldi, Kenneth Michelson, Mark Oskin, Andrew Petersen, Andrew Putnam, Andrew Schwerin, Steven Swanson
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Publication number: 20060179429Abstract: A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar.” WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i.e., a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks. Finally, a simple fence instruction is used to allow applications to handle relaxed memory consistency.Type: ApplicationFiled: November 22, 2005Publication date: August 10, 2006Applicant: University of WashingtonInventors: Susan Eggers, Martha Mercaldi, Kenneth Michelson, Mark Oskin, Andrew Petersen, Andrew Putnam, Andrew Schwerin, Steven Swanson