Abstract: Various embodiments disclose a system that includes a first source processor that generates a first stream of graphics data, a second source processor that generates a second stream of graphics data, a display device that displays at least one of the first stream of graphics data and the second stream of graphics data, and a timing controller that is coupled to the first source processor and the second source processor and receives a first control signal to enter into a self-refresh state, in response, enters into the self-refresh state, causes the display device to display a first frame stored in memory, wherein the first frame includes at least a portion of data included in the first stream of graphics data, receives a second stream of graphics data, exits the self-refresh state, and causes the display device to display the second stream of graphics data.

Abstract: Various embodiments disclose a system that includes a first source processor that generates a first stream of graphics data, a second source processor that generates a second stream of graphics data, a display device that displays at least one of the first stream of graphics data and the second stream of graphics data, and a timing controller that is coupled to the first source processor and the second source processor and receives a first control signal to enter into a self-refresh state, in response, enters into the self-refresh state, causes the display device to display a first frame stored in memory, wherein the first frame includes at least a portion of data included in the first stream of graphics data, receives a second stream of graphics data, exits the self-refresh state, and causes the display device to display the second stream of graphics data.

Abstract: A power subsystem is configured to manage the maximum power usage of a computer subsystem. A power detector determines when power usage approaches the maximum capability of the power supply. The power detector generates a signal that corresponds to power usage. A controller then applies the signal to the system voltage regulator as a secondary regulation function such that the output voltage is reduced in a manner that supports maximum operating voltage while limiting power usage to within the capability of the power supply. The controller may configure the signal to implement the secondary regulation function as a modification of the feedback voltage, the reference voltage, or the current feedback of the regulator. As a result the subsystem causes the computer subsystem to operate at an optimum point on the voltage-current curve of the power supply.

Abstract: A power subsystem is configured to manage the maximum power usage of a computer subsystem. A power detector determines when power usage approaches the maximum capability of the power supply. The power detector generates a signal that corresponds to power usage. A controller then applies the signal to the system voltage regulator as a secondary regulation function such that the output voltage is reduced in a manner that supports maximum operating voltage while limiting power usage to within the capability of the power supply. The controller may configure the signal to implement the secondary regulation function as a modification of the feedback voltage, the reference voltage, or the current feedback of the regulator. As a result the subsystem causes the computer subsystem to operate at an optimum point on the voltage-current curve of the power supply.

Abstract: A system and method are provided for decoding an audio signal. In one embodiment, a first pulse is identified with a predetermined relative duration with respect to a second pulse. A sampling frequency is then calculated based on such identification. In another embodiment, an audio signal is decoded utilizing a threshold. In still yet another embodiment, a decoder is provided for decoding an audio signal utilizing a clock that is independent of the audio signal.

Abstract: Embodiments of power management modes for memory devices are disclosed.

Abstract: An aspect of the invention relates to a method of dynamically adjusting power consumption of a random access memory (RAM) coupled to a processor. Frequency of a memory clock signal coupled to the RAM is reduced. At least one supply voltage coupled to the RAM is reduced. At least one latency parameter of the RAM is configured in response to the reduced frequency and the reduced at least one supply voltage. The RAM may then be re-initialized. In this manner, voltage supplied to the RAM is reduced, thereby reducing power consumption in the RAM.