Patents by Inventor Andrew R. Southworth

Andrew R. Southworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230209728
    Abstract: A process of fabricating an electromagnetic circuit includes providing three laminate sheets, forming a first feature in a first laminate sheet of the three laminate sheets, and forming a second feature in a second laminate sheet of the three laminate sheets. The second feature is aligned with the first feature when aligning the second laminate sheet with the first laminate sheet. The process further includes stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with the third laminate sheet. The first feature and the second feature define a contiguous element. The process further includes filling the contiguous element with an electrically conductive material to form an electrically continuous conductor.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 29, 2023
    Inventors: Mikhail Pevzner, Gregory G. Beninati, James E. Benedict, Andrew R. Southworth
  • Patent number: 11653484
    Abstract: An apparatus to automatically place layers of a printed circuit board on a fixture includes a robotic device having a base that is secured to a surface, an upright column that extends upwardly from the base, and a movable arm rotatably coupled to the upright column. The movable arm is configured to rotate about a vertical axis defined by the upright column. The movable arm is further configured to rotate from a position in which the movable arm is disposed over a laminate sheet fixture and to pick up a laminate sheet to a position in which the movable arm is disposed over a board layup fixture to deposit the laminate sheet in the board layup fixture, and from a position in which the movable arm is disposed over a bond film fixture and to pick up a bond film to a position in which the movable arm is disposed over the board layup fixture to deposit the bond film in the board layup fixture.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 16, 2023
    Assignee: RAYTHEON COMPANY
    Inventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Wade A. Schwanda
  • Publication number: 20230121347
    Abstract: Electromagnetic circuit structures and methods are provided for a circuit board that includes a hole disposed through a substrate to provide access to an electrical component, such as a signal trace line (or stripline), that is at least partially encapsulated (e.g., sandwiched) between substrates. The electrical component includes a portion substantially aligned with the hole, and an electrical conductor is disposed within the hole. The electrical conductor is soldered to the portion of the electrical component.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Inventors: Andrew R. Southworth, Thomas V. Sikina, John P. Haven, James E. Benedict, Kevin Wilder
  • Patent number: 11606865
    Abstract: A process of fabricating an electromagnetic circuit includes providing three laminate sheets, forming a first feature in a first laminate sheet of the three laminate sheets, and forming a second feature in a second laminate sheet of the three laminate sheets. The second feature is aligned with the first feature when aligning the second laminate sheet with the first laminate sheet. The process further includes stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with the third laminate sheet. The first feature and the second feature define a contiguous element. The process further includes filling the contiguous element with an electrically conductive material to form an electrically continuous conductor.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 14, 2023
    Assignee: RAYTHEON COMPANY
    Inventors: Mikhail Pevzner, Gregory G. Beninati, James E. Benedict, Andrew R. Southworth
  • Patent number: 11470725
    Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: October 11, 2022
    Assignee: RAYTHEON COMPANY
    Inventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Thomas V. Sikina, Kevin Wilder, Matthew Souza, Aaron Michael Torberg
  • Patent number: 11444365
    Abstract: A RAMP-radio frequency (RAMP-RF) assembly is provided and includes an RF panel including a microstrip interface, a plate including a stripline interface and a microstrip-to-stripline transition element operably connectable to the microstrip interface and to the stripline interface.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 13, 2022
    Assignee: RAYTHEON COMPANY
    Inventors: James Benedict, Erika Klek, John P. Haven, Michael Souliotis, Thomas V. Sikina, Andrew R. Southworth, Kevin Wilder
  • Patent number: 11375609
    Abstract: A radio frequency connector includes a substrate, a first ground plane disposed upon the substrate, a signal conductor having a first contact point, with the first contact point being configured to electrically mate with a second contact point, and a first ground boundary configured to electrically mate with a second ground boundary, with the first ground boundary being formed as an electrically continuous conductor within the substrate.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: June 28, 2022
    Assignee: RAYTHEON COMPANY
    Inventors: Thomas V. Sikina, James E. Benedict, John P. Haven, Andrew R. Southworth, Semira M. Azadzoi
  • Publication number: 20220052460
    Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.
    Type: Application
    Filed: October 26, 2021
    Publication date: February 17, 2022
    Inventors: Thomas V. Sikina, John P. Haven, James E. Benedict, Jonathan E. Nufio-Molina, Andrew R. Southworth
  • Publication number: 20210400820
    Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.
    Type: Application
    Filed: September 2, 2021
    Publication date: December 23, 2021
    Inventors: James E. Benedict, Gregory G. Beninati, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
  • Publication number: 20210368629
    Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.
    Type: Application
    Filed: August 6, 2021
    Publication date: November 25, 2021
    Inventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Thomas V. Sikina, Kevin Wilder, Matthew Souza, Aaron Michael Torberg
  • Patent number: 11171101
    Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 9, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: James E. Benedict, Paul A. Danello, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
  • Patent number: 11158955
    Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 26, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Thomas V. Sikina, John P. Haven, James E. Benedict, Jonathan E. Nufio-Molina, Andrew R. Southworth
  • Patent number: 11145952
    Abstract: A communications array includes a support structure configured to array elements, and a plurality of array elements supported by the support structure. Each array element is fabricated from an advanced manufacturing techniques (AMT) process. The support structure may be fabricated from a printed circuit board (PCB) or similar dielectric material. Each array element may include a radiator and/or a beamformer manufactured using the AMT process. The communications array further may include a copper vertical launch (CVL) and/or an electromagnetic boundary.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: October 12, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Thomas V. Sikina, John P. Haven, Kevin Wilder, James E. Benedict, Andrew R. Southworth, Mary K. Herndon
  • Patent number: 11145977
    Abstract: An array includes a support structure configured to support columns of beamformer assemblies, and a plurality of beamformer assemblies supported by the support structure. Each beamformer assembly includes at least one beamformer having at least one first beamformer segment and at least one second beamformer segment configured to interconnect with the first beamformer segment.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 12, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Kevin Wilder, Jonathan E. Nufio-Molina, Phillip W. Thiessen, Thomas V. Sikina, James E. Benedict, Andrew R. Southworth, Erika Klek
  • Publication number: 20210305187
    Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Inventors: James E. Benedict, Paul A. Danello, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
  • Publication number: 20210296751
    Abstract: A RAMP-radio frequency (RAMP-RF) assembly is provided and includes an RF panel including a microstrip interface, a plate including a stripline interface and a microstrip-to-stripline transition element operably connectable to the microstrip interface and to the stripline interface.
    Type: Application
    Filed: March 18, 2020
    Publication date: September 23, 2021
    Inventors: JAMES BENEDICT, Erika Klek, John P. Haven, Michael Souliotis, Thomas V. Sikina, Andrew R. Southworth, Kevin Wilder
  • Patent number: 11122692
    Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: September 14, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: James E. Benedict, Gregory G. Beninati, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
  • Patent number: 11109489
    Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 31, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Thomas V. Sikina, Kevin Wilder, Matthew Souza, Aaron Michael Torberg
  • Patent number: 11107610
    Abstract: A method includes blending a dielectric material including a titanate with a carbon-based ink to form a modified carbon-based ink. The method also includes printing the modified carbon-based ink onto a structure. The method further includes curing the printed modified carbon-based ink on the structure at a temperature that does not exceed about 250° C. In addition, the method includes processing the cured printed modified carbon-based ink to form a thick film resistor. Blending the dielectric material with the carbon-based ink causes the modified carbon-based ink to have a resistivity that is at least double a resistivity of the carbon-based ink.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 31, 2021
    Assignees: Raytheon Company, University of Massachusetts
    Inventors: Erika C. Klek, Mary K. Herndon, Thomas V. Sikina, James E. Benedict, Andrew R. Southworth, Kevin M. Wilder, Oshadha K. Ranasingha, Alkim Akyurtlu
  • Patent number: 11089687
    Abstract: A method of manufacturing a power divider circuit includes milling a conductive material disposed upon a first substrate to form a signal trace. The signal trace includes a division from a single trace to two arm traces, with each of the two arm traces having a proximal end electrically connected to the single trace and a distal end electrically connected to each of two secondary traces. The method further includes depositing a resistive ink between the two distal ends to form a resistive electrical connection between the two arm traces, bonding a second substrate to the first substrate to substantially encapsulate the traces between the first substrate and the second substrate, and milling through at least one of the first substrate or the second substrate to provide access to at least one of the traces. A signal divider is further disclosed.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 10, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: Jonathan E. Nufio-Molina, Thomas V. Sikina, James E. Benedict, Andrew R. Southworth, Semira M. Azadzoi