Patents by Inventor Andrew R. Southworth
Andrew R. Southworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230209728Abstract: A process of fabricating an electromagnetic circuit includes providing three laminate sheets, forming a first feature in a first laminate sheet of the three laminate sheets, and forming a second feature in a second laminate sheet of the three laminate sheets. The second feature is aligned with the first feature when aligning the second laminate sheet with the first laminate sheet. The process further includes stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with the third laminate sheet. The first feature and the second feature define a contiguous element. The process further includes filling the contiguous element with an electrically conductive material to form an electrically continuous conductor.Type: ApplicationFiled: February 23, 2023Publication date: June 29, 2023Inventors: Mikhail Pevzner, Gregory G. Beninati, James E. Benedict, Andrew R. Southworth
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Patent number: 11653484Abstract: An apparatus to automatically place layers of a printed circuit board on a fixture includes a robotic device having a base that is secured to a surface, an upright column that extends upwardly from the base, and a movable arm rotatably coupled to the upright column. The movable arm is configured to rotate about a vertical axis defined by the upright column. The movable arm is further configured to rotate from a position in which the movable arm is disposed over a laminate sheet fixture and to pick up a laminate sheet to a position in which the movable arm is disposed over a board layup fixture to deposit the laminate sheet in the board layup fixture, and from a position in which the movable arm is disposed over a bond film fixture and to pick up a bond film to a position in which the movable arm is disposed over the board layup fixture to deposit the bond film in the board layup fixture.Type: GrantFiled: November 8, 2019Date of Patent: May 16, 2023Assignee: RAYTHEON COMPANYInventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Wade A. Schwanda
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Publication number: 20230121347Abstract: Electromagnetic circuit structures and methods are provided for a circuit board that includes a hole disposed through a substrate to provide access to an electrical component, such as a signal trace line (or stripline), that is at least partially encapsulated (e.g., sandwiched) between substrates. The electrical component includes a portion substantially aligned with the hole, and an electrical conductor is disposed within the hole. The electrical conductor is soldered to the portion of the electrical component.Type: ApplicationFiled: December 20, 2022Publication date: April 20, 2023Inventors: Andrew R. Southworth, Thomas V. Sikina, John P. Haven, James E. Benedict, Kevin Wilder
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Patent number: 11606865Abstract: A process of fabricating an electromagnetic circuit includes providing three laminate sheets, forming a first feature in a first laminate sheet of the three laminate sheets, and forming a second feature in a second laminate sheet of the three laminate sheets. The second feature is aligned with the first feature when aligning the second laminate sheet with the first laminate sheet. The process further includes stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with the third laminate sheet. The first feature and the second feature define a contiguous element. The process further includes filling the contiguous element with an electrically conductive material to form an electrically continuous conductor.Type: GrantFiled: November 8, 2019Date of Patent: March 14, 2023Assignee: RAYTHEON COMPANYInventors: Mikhail Pevzner, Gregory G. Beninati, James E. Benedict, Andrew R. Southworth
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Patent number: 11470725Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.Type: GrantFiled: August 6, 2021Date of Patent: October 11, 2022Assignee: RAYTHEON COMPANYInventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Thomas V. Sikina, Kevin Wilder, Matthew Souza, Aaron Michael Torberg
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Patent number: 11444365Abstract: A RAMP-radio frequency (RAMP-RF) assembly is provided and includes an RF panel including a microstrip interface, a plate including a stripline interface and a microstrip-to-stripline transition element operably connectable to the microstrip interface and to the stripline interface.Type: GrantFiled: March 18, 2020Date of Patent: September 13, 2022Assignee: RAYTHEON COMPANYInventors: James Benedict, Erika Klek, John P. Haven, Michael Souliotis, Thomas V. Sikina, Andrew R. Southworth, Kevin Wilder
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Patent number: 11375609Abstract: A radio frequency connector includes a substrate, a first ground plane disposed upon the substrate, a signal conductor having a first contact point, with the first contact point being configured to electrically mate with a second contact point, and a first ground boundary configured to electrically mate with a second ground boundary, with the first ground boundary being formed as an electrically continuous conductor within the substrate.Type: GrantFiled: November 6, 2020Date of Patent: June 28, 2022Assignee: RAYTHEON COMPANYInventors: Thomas V. Sikina, James E. Benedict, John P. Haven, Andrew R. Southworth, Semira M. Azadzoi
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Publication number: 20220052460Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.Type: ApplicationFiled: October 26, 2021Publication date: February 17, 2022Inventors: Thomas V. Sikina, John P. Haven, James E. Benedict, Jonathan E. Nufio-Molina, Andrew R. Southworth
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Publication number: 20210400820Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.Type: ApplicationFiled: September 2, 2021Publication date: December 23, 2021Inventors: James E. Benedict, Gregory G. Beninati, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
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Publication number: 20210368629Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.Type: ApplicationFiled: August 6, 2021Publication date: November 25, 2021Inventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Thomas V. Sikina, Kevin Wilder, Matthew Souza, Aaron Michael Torberg
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Patent number: 11171101Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.Type: GrantFiled: March 31, 2020Date of Patent: November 9, 2021Assignee: RAYTHEON COMPANYInventors: James E. Benedict, Paul A. Danello, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
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Patent number: 11158955Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.Type: GrantFiled: November 7, 2018Date of Patent: October 26, 2021Assignee: RAYTHEON COMPANYInventors: Thomas V. Sikina, John P. Haven, James E. Benedict, Jonathan E. Nufio-Molina, Andrew R. Southworth
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Patent number: 11145952Abstract: A communications array includes a support structure configured to array elements, and a plurality of array elements supported by the support structure. Each array element is fabricated from an advanced manufacturing techniques (AMT) process. The support structure may be fabricated from a printed circuit board (PCB) or similar dielectric material. Each array element may include a radiator and/or a beamformer manufactured using the AMT process. The communications array further may include a copper vertical launch (CVL) and/or an electromagnetic boundary.Type: GrantFiled: November 14, 2019Date of Patent: October 12, 2021Assignee: RAYTHEON COMPANYInventors: Thomas V. Sikina, John P. Haven, Kevin Wilder, James E. Benedict, Andrew R. Southworth, Mary K. Herndon
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Patent number: 11145977Abstract: An array includes a support structure configured to support columns of beamformer assemblies, and a plurality of beamformer assemblies supported by the support structure. Each beamformer assembly includes at least one beamformer having at least one first beamformer segment and at least one second beamformer segment configured to interconnect with the first beamformer segment.Type: GrantFiled: June 14, 2019Date of Patent: October 12, 2021Assignee: RAYTHEON COMPANYInventors: Kevin Wilder, Jonathan E. Nufio-Molina, Phillip W. Thiessen, Thomas V. Sikina, James E. Benedict, Andrew R. Southworth, Erika Klek
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Publication number: 20210305187Abstract: A process of fabricating an electromagnetic circuit includes providing a first sheet of dielectric material including a top surface having at least one conductive trace and depositing a solder bump on the at least one conductive trace. The process further includes applying a second sheet of dielectric material to the first sheet of dielectric material with bond film sandwiched in between, the second sheet of dielectric material having a through-hole providing access to the solder bump. The process further includes bonding the first and second dielectric materials to one another and removing bond film resin from the solder bump. The process further includes machining the solder bump by the drilling or milling process to achieve a desired amount of solder in the solder bump.Type: ApplicationFiled: March 31, 2020Publication date: September 30, 2021Inventors: James E. Benedict, Paul A. Danello, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
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Publication number: 20210296751Abstract: A RAMP-radio frequency (RAMP-RF) assembly is provided and includes an RF panel including a microstrip interface, a plate including a stripline interface and a microstrip-to-stripline transition element operably connectable to the microstrip interface and to the stripline interface.Type: ApplicationFiled: March 18, 2020Publication date: September 23, 2021Inventors: JAMES BENEDICT, Erika Klek, John P. Haven, Michael Souliotis, Thomas V. Sikina, Andrew R. Southworth, Kevin Wilder
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Patent number: 11122692Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.Type: GrantFiled: June 11, 2020Date of Patent: September 14, 2021Assignee: RAYTHEON COMPANYInventors: James E. Benedict, Gregory G. Beninati, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
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Patent number: 11109489Abstract: An apparatus for automating the fabrication of a copper vertical launch (CVL) within a printed circuit board (PCB) includes a feed mechanism to feed and extrude copper wire from a spool of copper wire and a wire cutting and gripping mechanism to receive copper wire from the feed mechanism, cut and secure a segment of copper wire, insert the segment of copper wire into a hole formed within the PCB, solder an end of the segment of copper wire to a signal trace of the PCB, and flush cut an opposite end of the segment of the copper wire to a surface of the PCB. The wire cutting and gripping mechanism includes a wire cutter to flush cut the segment of copper wire and an integrated heated gripper device to receive the copper wire from the spool of copper wire and cut and grab a segment from copper wire.Type: GrantFiled: August 15, 2019Date of Patent: August 31, 2021Assignee: RAYTHEON COMPANYInventors: Mikhail Pevzner, James E. Benedict, Andrew R. Southworth, Thomas V. Sikina, Kevin Wilder, Matthew Souza, Aaron Michael Torberg
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Patent number: 11107610Abstract: A method includes blending a dielectric material including a titanate with a carbon-based ink to form a modified carbon-based ink. The method also includes printing the modified carbon-based ink onto a structure. The method further includes curing the printed modified carbon-based ink on the structure at a temperature that does not exceed about 250° C. In addition, the method includes processing the cured printed modified carbon-based ink to form a thick film resistor. Blending the dielectric material with the carbon-based ink causes the modified carbon-based ink to have a resistivity that is at least double a resistivity of the carbon-based ink.Type: GrantFiled: June 15, 2020Date of Patent: August 31, 2021Assignees: Raytheon Company, University of MassachusettsInventors: Erika C. Klek, Mary K. Herndon, Thomas V. Sikina, James E. Benedict, Andrew R. Southworth, Kevin M. Wilder, Oshadha K. Ranasingha, Alkim Akyurtlu
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Patent number: 11089687Abstract: A method of manufacturing a power divider circuit includes milling a conductive material disposed upon a first substrate to form a signal trace. The signal trace includes a division from a single trace to two arm traces, with each of the two arm traces having a proximal end electrically connected to the single trace and a distal end electrically connected to each of two secondary traces. The method further includes depositing a resistive ink between the two distal ends to form a resistive electrical connection between the two arm traces, bonding a second substrate to the first substrate to substantially encapsulate the traces between the first substrate and the second substrate, and milling through at least one of the first substrate or the second substrate to provide access to at least one of the traces. A signal divider is further disclosed.Type: GrantFiled: February 27, 2019Date of Patent: August 10, 2021Assignee: RAYTHEON COMPANYInventors: Jonathan E. Nufio-Molina, Thomas V. Sikina, James E. Benedict, Andrew R. Southworth, Semira M. Azadzoi