Abstract: The embodiment relates to special controls in a processor to prevent synonym entries in a translation lookaside buffer (DLAT) for a system which has DLAT entries that can concurrently translate virtual page addresses in multiple address spaces into real main storage page frame addresses. The controls use a synonym resolution register (SRR) which divides each address space in the system into common and private portions. Fields in the SRR indicate which portions are to be common to all address spaces, and which portions are private in each address space. A SRR control circuit selects a particular status field under control of a virtual address requesting main storage access. Each DLAT entry contains a common/private storage indicator which is controlled by the particular status field when the DLAT entry is loaded.