Abstract: A modular wing portion for installation into a wing assembly as a pre-assembled unit, the modular wing portion comprising at least one rib and at least one internal fuel tank system component, and a cartridge jig for the assembly of the modular wing portion away from an aircraft wing, the cartridge jig comprising a plurality of secondary support members, each secondary support member configured to receive and support a rib such that a fuel system component can be installed to the rib. Also an aircraft and wings, transport frames and methods of assembly.

Abstract: A host system includes a memory and a processing device coupled to the memory to perform operations including obtaining log data from a memory sub-system of a plurality of memory sub-systems, wherein the log data reflects memory usage of a memory device of the memory sub-system, wherein the memory device is shared by the plurality of host systems, including the host system, connected to the plurality of memory sub-systems; and determining, based on the log data, a schedule of a plurality of processes running on the plurality of host systems, wherein the plurality of processes share the memory device.

Abstract: A part is positioned between a display and an image capturing device pointed toward the display. A visual feedback loop is conducted using the display and the image capturing device to refine a part profile picture on the display corresponding to a profile of the part in an image captured by the image capturing device. The visual feedback loop recursively projects on a display screen an input picture containing a pattern region; captures images of the part while the display is displaying the input picture; based on the captured image, refines a picture that more closely corresponds to the profile of the part; and sets the refined image to be a next input image. The feedback loop iteratively refines the picture projected on the display screen until it becomes the part profile picture.

Abstract: Methods, systems, computer-readable media, devices, and apparatuses for synchronized mode transitions are presented. A first device configured to be worn at an ear includes a processor configured to, in a first contextual mode, receive a first mode change request from a second device to transition at a first time to a second contextual mode. The first mode change request is based on detection of a trigger condition. The processor is further configured to, at the first time, transition from the first contextual mode to the second contextual mode based on the first mode change request.

Abstract: A computer-implemented method includes receiving a task performance request; retrieving a stored task specification corresponding to the task performance request; generating a task implementation request including the stored task specification and an execution context; generating a task implementation corresponding to the task implementation request, the task implementation including a sequence of task execution commands; and causing execution of the sequence of task execution commands.

Abstract: A decision support method and system is provided for monitoring and treating pediatric obesity. Embodiments include generating obesity risk curves corresponding to obesity risk levels, for example, severe and morbid obesity risk levels. Generating obesity risk curves depends on predicting at least one health proxy such as, for example, spend data and chronic conditions. Generating severe obesity curves depends on an age-dependent multiplier. An obesity risk level is assigned to a target pediatric patient using the obesity risk curves dependent on the age-dependent multiplier. In some aspects, an intervening response is initiated based on the assigned obesity risk level.

Abstract: A method and apparatus for locating respective end regions of wires of an armour layer of a segment of flexible pipe body at a respective desired positions in an end fitting, and apparatus for terminating a segment of flexible pipe body in an end fitting are disclosed.

Abstract: Methods, systems, and devices for access heatmap generation at a memory device are described. In some examples, a memory device may maintain a register for tracking access operation occurrence, for which access operations of an address of the memory device may be mapped to multiple fields of the register. In some cases, in response to a first access operation performed on a first address of the memory device, the memory device may increment a first field and a second field of the register and, in response to a second access operation performed on a second address of the memory device, the memory device may increment the first field and a third field of the register. In some examples, the memory device may maintain a second register having a set of fields that each indicate a respective address for which an access occurrence satisfies a threshold.

Abstract: Disclosed in some examples are systems, devices, machine-readable mediums, and methods for customizing an in-memory versioning mode for each memory location according to a predicted access behavior to optimize memory device performance. Usage data in a previous time period may be utilized along with policy rules to determine whether to configure a particular memory address as a zero copy or direct copy mode. For example, memory addresses that are read frequently may be configured as direct copy mode to reduce the read latency penalty. This improves the functioning of the memory system by reducing read latency for memory addresses that are frequently read but written to less frequently, and reduces write latency for memory locations that are frequently written to, but not read as frequently.

Abstract: Methods, systems, and devices for performance monitoring for a memory system are described. A memory system may use a set of counters to determine state information for the memory system. The memory system may also use a set of timers to determine latency information for the memory system. In response to a request for performance information, the memory system may transmit state information, latency information, or both to a host system.

Abstract: To implement a multi-format data object in memory, a device can receive an allocation request for a data object that includes a set of data elements. This allocation request includes respective details for a set of formats for the data object, such as details for a first format in the set of formats including. The details can include memory address information and a mapping between a first data element of the data object in the first format to a second data element in a second format in the set of formats. The details can also include identification of a conversion function configured to convert the first data element to the second data element. The device can provide access to the second format of the data object from the first format of the data object in the memory based on the mapping data structure or the conversion data structure.

Abstract: A method and apparatus for locating respective end regions of wires of an armour layer of a segment of flexible pipe body at a respective desired positions in an end fitting, and apparatus for terminating a segment of flexible pipe body in an end fitting are disclosed.

Abstract: Methods, systems, and devices for techniques for data transfer between tiered memory devices are described. A memory system may include a data transfer engine to manage data transfers between different tiers of memory devices within the memory system. The data transfer engine may receive a command which includes a set of source addresses of each of a set of data sets and a set of destination addresses to which the data sets are to be transferred. The data transfer engine may schedule and perform a transfer operation to transfer each of the set of data sets from the respective source address to the respective destination address. The command may further include an indication of an interrupt policy of a set of interrupt policies supported by the data transfer engine. The set of interrupt policies may determine how the data transfer engine may handle interruptions to the data transfer operation.

Abstract: A system includes a memory device and a processing device coupled to the memory device, and the processing device is to perform operations including determining, by monitoring accesses to the memory device, a plurality of values of one or more memory usage statistics reflecting memory usage by a plurality of requestors connected to the memory sub-system; generating memory usage data by processing the plurality of values of the one or more memory usage statistics; and transmitting, to a requestor of the plurality of requestors, the memory usage data.

Abstract: Methods, systems, and devices for inter-tier metadata storage are described. A controller associated with a memory system may manage metadata storage across tiers of memory within the memory system or across memory systems. The controller may transfer metadata between tiers of memory based on whether an access count associated with the metadata satisfies a threshold. For example, the controller may transfer metadata from a first tier of memory to a second tier of memory if the access count satisfies a threshold count. The controller may transfer the metadata from the second tier of memory to the first tier of memory if the access count fails to satisfy the threshold count.

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. A controller of a memory system may facilitate data rearrangement within a block-addressable memory device based on metadata associated with prefetching data to a byte-addressable memory device or to a host system. For example, the controller may utilize the metadata and various access commands to rearrange associated data within the block-addressable memory device such that the data is written to a singular superblock of the block-addressable memory device. In some examples, one or more counters may be utilized by the controller to determine whether to rearrange the data within the block-addressable memory device.

Abstract: An access counter associated with a segment of a memory device is maintained. The segment comprises a plurality of lines. A first count of the plurality of lines is identified. A subset of the plurality of lines of the segment is monitored. A second count of the subset of the plurality of lines is identified. An access notification for a first line of the subset of the plurality of lines is received. A first value of the access counter is changed by a second value. The second value is weighted based on the first count and the second count. Based on the first value of the access counter, a memory management scheme is implemented.

Abstract: Systems, devices, and methods related to a deep learning accelerator and memory are described. For example, the accelerator can have processing units to perform at least matrix computations of an artificial neural network via execution of instructions. The processing units have a local memory store operands of the instructions. The accelerator can access a random access memory via a system buffer, or without going through the system buffer. A fetch instruction can request an item, available at a memory address in the random access memory, to be loaded into the local memory at a local address. The fetch instruction can include a hint for the caching of the item in the system buffer. During execution of the instruction, the hint can be used to determine whether to load the item through the system buffer or to bypass the system buffer in loading the item.

Abstract: Methods, systems, and devices for access heatmap generation at a memory device are described. In some examples, a memory device may maintain a register for tracking access operation occurrence, for which access operations of an address of the memory device may be mapped to multiple fields of the register. In some cases, in response to a first access operation performed on a first address of the memory device, the memory device may increment a first field and a second field of the register and, in response to a second access operation performed on a second address of the memory device, the memory device may increment the first field and a third field of the register. In some examples, the memory device may maintain a second register having a set of fields that each indicate a respective address for which an access occurrence satisfies a threshold.

Abstract: Devices and methods are disclosed, including receiving, by a memory controller of a memory device, a memory request from a host device; collecting packet trace data from the memory request; including the packet trace data in a log stored in a memory array of the memory device; and returning the log to the host device.