Abstract: A phase lock detector circuit for detecting the lock state of a phase locked loop (PLL) such that it is known when a synthesized clock has achieved a stable phase relationship with its reference clock signal. The PLL includes an input for receiving the reference signal, a digital phase detector, a voltage controlled oscillator, and a frequency divider. The phase lock detector of the present invention includes a loss of lock detector (LOLD) connected to the frequency divider, the phase detector and the input. The LOLD detects the occurrence of a selected phase difference between the reference signal and an output of the frequency divider for a selected number of cycles. Also included is a gain of lock detector (GOLD) connected to the frequency divider and the input. The GOLD detects the occurrence of the reference signal within a selected phase difference of an output of the frequency divider for a second selected number of cycles.

Abstract: A processor and disk controller are arranged to operate with either of two types of disk drive, a drive for a five and one-fourth inch disk or a drive for an eight inch disk, and a method and apparatus are provided to test a port to detect which type disk is connected. The disk drives do not directly signal their type, and in one operation this information is derived from "drive ready", signals that are supplied separately by each disk type. In an alternative method and apparatus, this information is derived by a test in which the clock speed is changed.

Abstract: An adaptively stretched clock input feature is provided on a natively synchronous DMAC device to make it support data transfers in an asynchronous bus environment. This feature effects adjustment of the DMAC transfer strobe access window as a function of data transfer (DTACK) timing. A late DTACK signal causes stretch of the clock controlled TXSTB transfer strobe to a length which will accommodate worst case memory access conditions of the asynchronous bus structure.

Abstract: Circuitry is provided to be used in association with a single transfer mode DMAC device to enable a programmer to control the number of bytes transferred during a DMA transfer cycle. The circuitry receives a coded mode control message from the microprocessor before transferring control of the data and address busses to the DMAC and generates one or both of two data transfer strobe signals which instruct the memory to transfer contiguous bytes, contiguous high alternate order bytes, or contiguous low alternate order bytes, or both.