Patents by Inventor Andrew Sawle

Andrew Sawle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210036610
    Abstract: A method of manufacturing a power semiconductor system includes providing a power module having one or more power transistor dies and attaching an inductor module to the power module such that the inductor module is electrically connected to a node of the power module. The inductor module includes a substrate with a magnetic material and windings at one or more sides of the substrate. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 4, 2021
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Patent number: 10833583
    Abstract: A method of manufacturing a power semiconductor system includes providing a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board and attaching an inductor module to the power stage module such that the inductor module is electrically connected to an output node of the power stage module. The inductor module includes a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: November 10, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Publication number: 20200212798
    Abstract: A method of manufacturing a power semiconductor system includes providing a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board and attaching an inductor module to the power stage module such that the inductor module is electrically connected to an output node of the power stage module. The inductor module includes a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Further methods of manufacturing power semiconductor systems and methods of manufacturing inductor modules are also described.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Patent number: 10601314
    Abstract: A power semiconductor system includes a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board, and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor is formed from a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Corresponding methods of manufacturing the power semiconductor system and the inductor module are also disclosed.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Publication number: 20190081562
    Abstract: A power semiconductor system includes a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board, and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor is formed from a ferrite sheet embedded in a second printed circuit board and windings patterned into the second printed circuit board. Corresponding methods of manufacturing the power semiconductor system and the inductor module are also disclosed.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Inventors: Petteri Palm, Frank Daeche, Zeeshan Umar, Andrew Sawle, Maciej Wojnowski, Xaver Schloegel, Josef Hoeglauer
  • Patent number: 9852939
    Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Martin Standing, Andrew Sawle, Matthew P. Elwin, David P. Jones, Martin Carroll, Ian Glenville Wagstaffe
  • Patent number: 9852940
    Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: December 26, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Martin Standing, Andrew Sawle, Matthew P. Elwin, David P. Jones, Martin Carroll, Ian Glenville Wagstaffe
  • Patent number: 8368211
    Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: February 5, 2013
    Assignee: International Rectifier Corporation
    Inventors: Martin Standing, Andrew Sawle, Matthew P Elwin, David P Jones, Martin Carroll, Ian Glenville Wagstaffe
  • Patent number: 7402507
    Abstract: A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: July 22, 2008
    Assignee: International Rectifier Corporation
    Inventors: Martin Standing, Mark Pavier, Robert J. Clarke, Andrew Sawle, Kenneth McCartney
  • Publication number: 20070158796
    Abstract: A semiconductor package that includes a semiconductor device that is integrated with a silicon substrate.
    Type: Application
    Filed: December 8, 2006
    Publication date: July 12, 2007
    Inventor: Andrew Sawle
  • Publication number: 20070108585
    Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
    Type: Application
    Filed: November 10, 2006
    Publication date: May 17, 2007
    Inventors: Mark Pavier, Andrew Sawle, Martin Standing
  • Publication number: 20070091546
    Abstract: An apparatus for coupling a plurality of surface mounted semiconductor device packages to a circuit board is provided. Each package including a semiconductor device die and a metal clip including a flat web portion having a bottom surface and at least one peripheral rim portion extending from an edge of said flat web portion, said bottom surface having solderable planar metal electrodes or pads on its bottom surface, the contact pads being formed in plurality of layouts having one or more columns and one or more rows. The apparatus including a circuit board contact pattern including one or more columns and one or more rows of contacts, a number of rows being equal to a largest number of contact pad rows in the plurality of contact pad layouts, a number of columns being equal to a largest number of contact pad columns in the plurality of contact pad layouts. The circuit board contact pattern is usable by all of the plurality of the contact pad layouts of the plurality of semiconductor device packages.
    Type: Application
    Filed: October 23, 2006
    Publication date: April 26, 2007
    Applicant: International Rectifier Corporation
    Inventors: Martin Standing, Andrew Sawle
  • Publication number: 20070052099
    Abstract: A semiconductor device includes a die with at least one electrode on a surface thereof, at least one solderable contact formed on the electrode, and a passivation layer formed over the electrode and including an opening that exposes the solderable contact. The passivation layer opening may be wider than the solderable contact such that a gap extends between the contact and the passivation layer. The device also includes a barrier layer disposed on the top surface of the electrode, and along the underside of the solderable contact and across the gap. The barrier layer may also extend under the passivation layer and may cover the entire top surface of the electrode. The barrier layer may also extend along the sidewalls of the electrode. The barrier layer may include a titanium layer or a titanium layer and nickel layer. The barrier layer protects the electrode and underlying die from acidic fluxes found in lead-free solders.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 8, 2007
    Inventors: Martin Carroll, David Jones, Andrew Sawle, Martin Standing
  • Publication number: 20060267183
    Abstract: A circuit board includes at least one trace having at least one heat spreader disposed thereon, the heater spreader being formed of a solidified paste, such as a paste that includes a mixture of binder particles and filler particles, or a solder paste. As an example, the heater spreader may be configured to increase a cross-sectional area of a portion of the trace, thereby improving heat flow along that portion of the trace. Alternatively, the heater spreader may be configured to increase the surface area of the trace, thereby increasing heat dissipation from the circuit board. As another example, the heat spreader may be disposed between the trace and a semiconductor device and thereby function as a heat sink for the device.
    Type: Application
    Filed: April 19, 2006
    Publication date: November 30, 2006
    Inventor: Andrew Sawle
  • Publication number: 20060249836
    Abstract: A semiconductor package including a conductive clip preferably in the shape of a can, a semiconductor die, and a conductive stack interposed between the die and the interior of the can which includes a conductive platform and a conductive adhesive body.
    Type: Application
    Filed: April 21, 2006
    Publication date: November 9, 2006
    Inventors: Andy Farlow, Mark Pavier, Andrew Sawle, George Pearson, Martin Standing
  • Publication number: 20060205112
    Abstract: A semiconductor package fabrication method in which drop on demand deposition of a drop on demand depositable material is used to prepare one component or a plurality of components of a semiconductor package or multi-chip module.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 14, 2006
    Inventors: Martin Standing, Mark Pavier, Robert Clarke, Andrew Sawle, Kenneth McCartney
  • Publication number: 20050269677
    Abstract: A semiconductor device which includes a power electrode on a surface thereof, a solderable body on the power electrode and a passivation body spaced from but surrounding the solderable body.
    Type: Application
    Filed: May 26, 2005
    Publication date: December 8, 2005
    Inventors: Martin Standing, Andrew Sawle, David Jones, Martin Carroll, Matthew Elwin
  • Publication number: 20050224960
    Abstract: A semiconductor package according to the present invention includes a metal can which receives in its interior space a MOSFET. The MOSFET so received is oriented such that its drain electrode is facing the bottom of the can and is electrically connected to the same by a layer of conductive epoxy or a solder or the like. The edges of the MOSFET so placed are spaced from the walls of the can. The space between the edges of the MOSFET and the walls of the can is filled with an insulating layer. A surface of the MOSFET is sub-flush below the plane of a substrate by 0.001-0.005 inches to reduce temperature cycling failures.
    Type: Application
    Filed: June 7, 2005
    Publication date: October 13, 2005
    Inventors: Martin Standing, Andrew Sawle
  • Publication number: 20050200011
    Abstract: A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites.
    Type: Application
    Filed: November 5, 2004
    Publication date: September 15, 2005
    Inventors: Martin Standing, Andrew Sawle, Matthew Elwin, David Jones, Martin Carroll, Ian Wagstaffe