Abstract: A processor and method for efficiently implementing matrix multiplication. The processor comprises: a first register (vC) for storing elements of an input vector (X); a second register (vB) for storing a plurality of index tuples, each index tuple comprising at least an input index addressing an element of the input vector (X) in the first register (vC); an output register (vA) comprising a plurality of accumulators for storing elements of an output vector (V); a vector unit configured to execute each index tuple in the second register (vB) in parallel by, for each index tuple: i) generating a respective result value by multiplying the element of the input vector (X) in the first register (vC) addressed by the input index of that index tuple by a corresponding kernel weight in a memory; and ii) adding the result value for that index tuple to one of the accumulators in the output register (vA).

Abstract: A processor (101) with an instruction set comprising a looping instruction and corresponding method are provided. The looping instruction is defined by a corresponding opcode and comprises a register operand for holding a sequence of subinstructions. The looping instruction causes the processor (101) to: repeatedly execute the looping instruction without incrementing a program counter, each execution of the looping instruction comprising: executing one of the subinstructions in the register operand; and modifying the register operand to contain a different set of subinstructions.

Abstract: Techniques for determining an inner product between a non-binarized first array and a second array using a binary logic unit are provided. The first array is decomposed into a plurality of binarized arrays by determining a respective binarized vector representation of each element of the first array in a vector basis having a set of basis vectors. Each binarized array comprises the binarized values corresponding to the same basis vector from each of the binarized vector representations. The binary logic unit is used to determine a respective result equal to the inner product of the second array and each respective one of the plurality of binarized arrays. The results are combined into an output by summing the results each weighted by the respective basis vector of the binarized array used to generate that result.

Abstract: A system comprising a microphone arranged to capture sound from an environment, and an ultrasound emitter configured to emit an emitted ultrasound signal into an environment. The microphone is arranged to capture a received audio signal from the environment, comprising a component in the human audible range. The microphone is also arranged to capture a received ultrasound signal comprising reflections of the emitted ultrasound signal, or else the system comprises another, co-located microphone arranged to capture the received ultrasound signal. Either way, the system further comprises a controller implemented in software or hardware or a combination thereof, wherein the controller is configured to process the received audio signal in dependence on the received ultrasound signal.

Abstract: A system comprising a microphone arranged to capture sound from an environment, and an ultrasound emitter configured to emit an emitted ultrasound signal into an environment. The microphone is arranged to capture a received audio signal from the environment, comprising a component in the human audible range. The microphone is also arranged to capture a received ultrasound signal comprising reflections of the emitted ultrasound signal, or else the system comprises another, co-located microphone arranged to capture the received ultrasound signal. Either way, the system further comprises a controller implemented in software or hardware or a combination thereof, wherein the controller is configured to process the received audio signal in dependence on the received ultrasound signal.

Abstract: A system comprising a microphone arranged to capture sound from an environment, and an ultrasound emitter configured to emit an emitted ultrasound signal into an environment. The microphone is arranged to capture a received audio signal from the environment, comprising a component in the human audible range. The microphone is also arranged to capture a received ultrasound signal comprising reflections of the emitted ultrasound signal, or else the system comprises another, co-located microphone arranged to capture the received ultrasound signal. Either way, the system further comprises a controller implemented in software or hardware or a combination thereof, wherein the controller is configured to process the received audio signal in dependence on the received ultrasound signal.

Abstract: A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.

Abstract: A processing apparatus comprising: a bus; a first processor connected to the bus and configured to communicate over the bus according to a bus protocol; a second, multithread processor; and an inter-thread interconnect based on a system of channels. The apparatus also comprises an interface between the bus and the inter-thread interconnect, comprising a bus side implementing the bus protocol and an interconnect side for interfacing with the system of channels. The first processor is thereby operable to communicate with a designated one of said threads via the bus and a respective channel of the inter-thread interconnect.

Abstract: A method and corresponding tool, the method comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by matching a plurality of the lower-level nodes and edges to higher-level structure nodes representing internal structure, each higher-level structure node representing a group of one or more lower-level nodes and one or more associated edges; and using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor. The higher-level structure nodes are selected exclusively from a predetermined set of structure node patterns, each pattern in the set having at most one entry point and at most one exit point.

Abstract: A method and corresponding tool for estimating program execution time. A higher-level structure is received as an input, representing control flow through an executable program. The higher-level structure comprises one or more levels of parent nodes, each parent node representing internal structure comprising a group of one or more child nodes and one or more associated edges between nodes. The levels of the higher-level structure are probed to extract a substructure representing a route through the program from a start instruction to an end instruction, by selectively extracting nodes of different levels of parent to represent different regions along the route in dependence on a location of the start and end instructions relative to the levels of parent nodes. An execution time for the route through the program is estimated based on the extracted substructure, and a modification affecting the execution time is made in dependence on the estimation.

Abstract: A method and corresponding tool, the method comprising: receiving as an input (a) a higher-level structure representing control flow through an executable program, the higher-level structure comprising one or more levels of parent nodes, each parent node representing internal structure comprising a group of one or more child nodes and one or more associated edges between nodes; and (b) an indication of at least one start and end instruction. The method further comprises probing the levels of the higher-level structure to extract a substructure representing a route through the program from the start to the end instruction, by selectively extracting nodes of different levels of parent to represent different regions along the route in dependence on a location of the start and end instructions relative to the levels of parent nodes; and based on the extracted substructure, estimating an execution time for the route through the program.

Abstract: A method and corresponding tool, the method comprising: generating a lower-level control flow structure representing a portion of an executable program, the lower-level control flow structure comprising a plurality of lower-level nodes representing operations occurring within the program and a plurality of directional edges representing program flow between nodes; generating a higher-level control flow structure by matching a plurality of the lower-level nodes and edges to higher-level structure nodes representing internal structure, each higher-level structure node representing a group of one or more lower-level nodes and one or more associated edges; and using the higher-level control flow structure to estimate a timing property relating to execution of the program on a processor. The higher-level structure nodes are selected exclusively from a predetermined set of structure node patterns, each pattern in the set having at most one entry point and at most one exit point.