Patents by Inventor Andrew Stanley Potemski

Andrew Stanley Potemski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8413103
    Abstract: Embodiments of a computer system, a method, a graphical user interface and a computer-program product (i.e., software) for use with the computer system are described. A chip designer may use these devices and techniques to configure and monitor the execution of tasks in a user-configurable electronic-design-automation (EDA) flow associated with a circuit or chip design. In particular, using an intuitive and interactive graphical user interface in EDA software, the chip designer can configure and initiate execution of the EDA flow. Then, during execution of EDA tasks in the EDA flow, an execution monitor in the graphical user interface may provide a graphical representation of real-time execution status information for the EDA tasks. Moreover, using the EDA software, the chip designer can debug the circuit or chip design if any errors or problems occur.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: April 2, 2013
    Assignee: Synopsys, Inc.
    Inventors: Andrew Stanley Potemski, John Scott Tyson, Steven Robert Eustes
  • Patent number: 8225256
    Abstract: Some embodiments of the present invention provide systems and techniques that accelerate project start and tape-out. During operation, a system can receive a set of technology files and a set of libraries. Next, the system can identify deficiencies in the set of technology files and the set of libraries. The system can then construct update utilities that when executed by a computer system cause the computer system to fix the deficiencies in the technology files and the set of libraries. Further, a system can receive a set of checks that are performed by a foundry. Next, the system can construct tape-out scripts that when executed by a computer cause the computer to perform the set of checks on the circuit design. The update utilities and the tape-out scripts can then be provided to a customer with an electronic design automation software to accelerate project start and tape-out.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: July 17, 2012
    Assignee: Synopsys, Inc.
    Inventors: Andrew Stanley Potemski, John Scott Tyson
  • Publication number: 20100235795
    Abstract: Embodiments of a computer system, a method, a graphical user interface and a computer-program product (i.e., software) for use with the computer system are described. A chip designer may use these devices and techniques to configure and monitor the execution of tasks in a user-configurable electronic-design-automation (EDA) flow associated with a circuit or chip design. In particular, using an intuitive and interactive graphical user interface in EDA software, the chip designer can configure and initiate execution of the EDA flow. Then, during execution of EDA tasks in the EDA flow, an execution monitor in the graphical user interface may provide a graphical representation of real-time execution status information for the EDA tasks. Moreover, using the EDA software, the chip designer can debug the circuit or chip design if any errors or problems occur.
    Type: Application
    Filed: April 15, 2009
    Publication date: September 16, 2010
    Applicant: SYNOPSYS, INC.
    Inventors: Andrew Stanley Potemski, John Scott Tyson, Steven Robert Eustes
  • Publication number: 20100235801
    Abstract: Some embodiments of the present invention provide systems and techniques that accelerate project start and tape-out. During operation, a system can receive a set of technology files and a set of libraries. Next, the system can identify deficiencies in the set of technology files and the set of libraries. The system can then construct update utilities that when executed by a computer system cause the computer system to fix the deficiencies in the technology files and the set of libraries. Further, a system can receive a set of checks that are performed by a foundry. Next, the system can construct tape-out scripts that when executed by a computer cause the computer to perform the set of checks on the circuit design. The update utilities and the tape-out scripts can then be provided to a customer with an electronic design automation software to accelerate project start and tape-out.
    Type: Application
    Filed: April 15, 2009
    Publication date: September 16, 2010
    Applicant: SYNOPSYS, INC.
    Inventors: Andrew Stanley Potemski, John Scott Tyson
  • Patent number: D628207
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: November 30, 2010
    Assignee: Synopsys, Inc.
    Inventors: Andrew Stanley Potemski, John Scott Tyson, Steven Robert Eustes
  • Patent number: D628208
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: November 30, 2010
    Assignee: Synopsys, Inc.
    Inventors: Andrew Stanley Potemski, John Scott Tyson, Matthew Robert Gutierrez