Abstract: Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.

Abstract: Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level.

Abstract: Provided are superconducting tunnel junctions, such as Josephson tunnel junctions, and a method of fabricating thereof. A junction includes an insulator disposed between two superconductors. The junction may also include one or two interface layers, with each interface layer disposed between the insulator and one of the superconductors. The interface layer is configured to prevent oxygen from entering the adjacent superconductor during fabrication and operation of the junction. Furthermore, the interface layer may protect the insulator from the environment during handling and processing of the junction, thereby allowing vacuum breaks after the interface layer is formed as well as new integration schemes, such as depositing a dielectric layer and forming a trench in the dielectric layer for the second superconductor. In some embodiments, the junction may be annealed during its fabrication to move oxygen from the superconductors and/or from the insulator into the one or two interface layers.

Abstract: Provided are methods of forming low resistivity contacts. Also provided are devices having such low resistive contacts. A method may include doping the surface of a structure, such as a gallium nitride layer. Specifically, a dopant containing layer is formed on the surface of the structure using, for example, atomic layer deposition (ALD). The dopant may magnesium. In some embodiments, the dopant containing layer also includes nitrogen. A capping layer may be then formed over the dopant containing layer to prevent dopant desorption. The stack including the structure with the dopant containing layer disposed on its surface is then annealed to transfer dopant from the dopant containing layer into the surface. After annealing, any remaining dopant containing layer is removed. When another component is later formed over the surface, a low resistivity contact is created between this other component and the doped structure.

Abstract: An amorphous silicon (a-Si) dielectric for superconducting electronics is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. Complete layers or thinner sub-layers of a-Si are formed by physical vapor deposition at low temperatures (<350 C, e.g. ˜200 C) to prevent reaction with superconducting materials, then exposed to fluorine. The fluorine may be a component of a gas or plasma, or it may be a component of an interface layer. The fluorine is driven into the a-Si by heat (e.g., <350 C) or impact to passivate defects such as dangling bonds.

Abstract: Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level.

Abstract: A tunnel barrier layer in a superconducting device, such as a Josephson junction, is made from catalytically grown silicon dioxide at a low temperature (<100 C, e.g., 20-30 C) that does not facilitate oxidation or silicide formation at the superconducting electrode interface. The tunnel barrier begins as a silicon layer deposited on a superconducting electrode and covered by a thin, oxygen-permeable catalytic layer. Oxygen gas is dissociated on contact with the catalytic layer, and the resulting oxygen atoms pass through the catalytic layer to oxidize the underlying silicon. The reaction self-limits when all the silicon is converted to silicon dioxide.

Abstract: Amorphous silicon (a-Si) is hydrogenated for use as a dielectric (e.g., an interlayer dielectric) for superconducting electronics. A hydrogenated a-Si layer is formed on a substrate by CVD or sputtering. The hydrogen may be integrated during or after the a-Si deposition. After the layer is formed, it is first annealed in an environment of high hydrogen chemical potential and subsequently annealed in an environment of low hydrogen chemical potential. Optionally, the a-Si (or an H-permeable overlayer, if added) may be capped with a hydrogen barrier before removing the substrate from the environment of low hydrogen chemical potential.

Abstract: A dielectric for superconducting electronics (e.g., amorphous silicon, silicon oxide, or silicon nitride) is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. A fluorinant (gas or plasma) is injected into a process chamber, either continuously or as a series of pulses, while the dielectric is being formed by chemical vapor deposition on a substrate. To further reduce defects, the silicon may be deposited from a silicon precursor that includes multiple co-bonded silicon atoms, such as disilane or trisilane.

Abstract: An amorphous silicon (a-Si) dielectric for superconducting electronics is fabricated with reduced loss tangent by fluorine passivation throughout the bulk of the layer. Complete layers or thinner sub-layers of a-Si are formed by physical vapor deposition at low temperatures (<350 C, e.g. ˜200 C) to prevent reaction with superconducting materials, then exposed to fluorine. The fluorine may be a component of a gas or plasma, or it may be a component of an interface layer. The fluorine is driven into the a-Si by heat (e.g., <350 C) or impact to passivate defects such as dangling bonds.

Abstract: A tunnel barrier layer in a superconducting device, such as a Josephson junction, is made from catalytically grown silicon dioxide at a low temperature (<100 C, e.g., 20-30 C) that does not facilitate oxidation or silicide formation at the superconducting electrode interface. The tunnel barrier begins as a silicon layer deposited on a superconducting electrode and covered by a thin, oxygen-permeable catalytic layer. Oxygen gas is dissociated on contact with the catalytic layer, and the resulting oxygen atoms pass through the catalytic layer to oxidize the underlying silicon. The reaction self-limits when all the silicon is converted to silicon dioxide.

Abstract: Computer-implemented methods for inspecting and/or classifying a wafer are provided. One computer-implemented includes detecting defects on a wafer using one or more defect detection parameters, which are determined based on a non-spatially localized characteristic of the wafer that is determined using output responsive to light scattered from the wafer generated by an inspection system. Another computer-implemented method includes classifying a wafer based on a combination of a non-spatially localized characteristic of the wafer determined using output responsive to light scattered from the wafer generated by an inspection system and a spatially localized characteristic of the wafer determined using the output.

Abstract: Computer-implemented methods for inspecting and/or classifying a wafer are provided. One computer-implemented includes detecting defects on a wafer using one or more defect detection parameters, which are determined based on a non-spatially localized characteristic of the wafer that is determined using output responsive to light scattered from the wafer generated by an inspection system. Another computer-implemented method includes classifying a wafer based on a combination of a non-spatially localized characteristic of the wafer determined using output responsive to light scattered from the wafer generated by an inspection system and a spatially localized characteristic of the wafer determined using the output.

Abstract: Methods and systems for detecting pinholes in a film formed on a wafer or for monitoring a thermal process tool are provided. One method for detecting pinholes in a film formed on a wafer includes generating output responsive to light from the wafer using an inspection system. The output includes first output corresponding to defects on the wafer and second output that does not correspond to the defects. This method also includes detecting the pinholes in the film formed on the wafer using the second output. One method for monitoring a thermal process tool includes generating output responsive to light from a wafer using an inspection system. The output includes the first and second output described above. The wafer was processed by the thermal process tool prior to generating the output. The method also includes monitoring the thermal process tool using the second output.

Abstract: Methods and systems for detecting pinholes in a film formed on a wafer or for monitoring a thermal process tool are provided. One method for detecting pinholes in a film formed on a wafer includes generating output responsive to light from the wafer using an inspection system. The output includes first output corresponding to defects on the wafer and second output that does not correspond to the defects. This method also includes detecting the pinholes in the film formed on the wafer using the second output. One method for monitoring a thermal process tool includes generating output responsive to light from a wafer using an inspection system. The output includes the first and second output described above. The wafer was processed by the thermal process tool prior to generating the output. The method also includes monitoring the thermal process tool using the second output.

Abstract: A fuel cell sub-assembly includes first and second flow field plates each comprising several fastener apertures defined at a number of fastening locations. A membrane electrode assembly is situated between the first and second flow field plates and includes several fastener apertures defined at a number of fastening locations, the respective fastener apertures aligned to define fastening holes. A form-in-place fastener formed of an elastomeric material is disposed in each of the fastening holes. The elastomeric material facilitates volumetric displacement of the form-in-place fasteners in response to placing the fuel cell sub-assembly in compression.

Abstract: A technique includes pulse width modulating an illuminating beam of a light to establish a pixel intensity and modulating the illuminating beam to create different tonal resolution ranges for the pixel intensity.

Abstract: A technique includes pulse width modulating a beam of a light to establish a pixel intensity. The technique includes controlling a light source to modulate an illumination of the beam to create different tonal resolution ranges for the pixel intensity.

Abstract: A fuel cell cathode catalyst is provided which comprises nanostructured elements comprising microstructured support whiskers bearing nanoscopic catalyst particles. The nanoscopic catalyst particles are made by the alternating application of first and second layers, the first layer comprising platinum and the second layer being an alloy or intimate mixture of iron and a second metal selected from the group consisting of Group VIb metals, Group VIIb metals and Group VIIIb metals other than platinum and iron, where the atomic ratio of iron to the second metal in the second layer is between 0 and 10, where the planar equivalent thickness ratio of the first layer to the second layer is between 0.3 and 5, and wherein the average bilayer planar equivalent thickness of the first and second layers is less than 100 ?.