Abstract: One embodiment of the present invention provides a system that performs a fast-scanning operation to generate fetch bundles within an instruction fetch unit (IFU) of a processor. During operation, the system obtains a cache line containing instructions at the IFU. Next, the system performs a complete-scanning operation on the cache line to identify control transfer instructions (CTIs) in the cache line. At the same time, the system performs a fast-scanning operation to identify CTIs in a group of initial instructions in the cache line, wherein the initial instructions are executed before other instructions in the cache line. Next, the system obtains results from the fast-scanning operation before results of the complete-scanning operation are available. The system then uses results from the fast-scanning operation to form an initial fetch bundle containing initial instructions, and sends the initial fetch bundle to the instruction-issue unit.

Abstract: One embodiment of the present invention provides a system that handles instruction fetch requests that return out-of-order at an IFU of a processor. During operation, the system sends a request to obtain a cache line to an instruction cache, wherein the request can be serviced and the cache line can be sent to a fetch buffer before a preceding cache line for a preceding request has returned from the instruction cache. In response to the request, the system receives the cache line from the instruction cache. Next, the system determines whether the cache line was returned out-of-order with respect to the preceding cache line. If so, the system performs an action to handle the out-of-order return.

Abstract: One embodiment of the present invention provides a system that handles instruction fetch requests that return out-of-order at an IFU of a processor. During operation, the system sends a request to obtain a cache line to an instruction cache, wherein the request can be serviced and the cache line can be sent to a fetch buffer before a preceding cache line for a preceding request has returned from the instruction cache. In response to the request, the system receives the cache line from the instruction cache. Next, the system determines whether the cache line was returned out-of-order with respect to the preceding cache line. If so, the system performs an action to handle the out-of-order return.

Abstract: One embodiment of the present invention provides a system that performs a fast-scanning operation to generate fetch bundles within an instruction fetch unit (IFU) of a processor. During operation, the system obtains a cache line containing instructions at the IFU. Next, the system performs a complete-scanning operation on the cache line to identify control transfer instructions (CTIs) in the cache line. At the same time, the system performs a fast-scanning operation to identify CTIs in a group of initial instructions in the cache line, wherein the initial instructions are executed before other instructions in the cache line. Next, the system obtains results from the fast-scanning operation before results of the complete-scanning operation are available. The system then uses results from the fast-scanning operation to form an initial fetch bundle containing initial instructions, and sends the initial fetch bundle to the instruction-issue unit.