Abstract: A memory circuit comprises a plurality of memory cells (2) arranged in rows and columns, the cells in each row being connected to a common wordline (4) and the cells in each column being connected between a pair of bit lines (6,8) across which a voltage differential is developed when a memory cell is accessed to be read; and a timing circuit (16) for producing a timing signal to control further circuitry in dependence on said voltage differential achieving a predetermined value. The memory circuit has a dummy bit line connected to a column of dummy cells, each dummy cell having the same structure as a memory cell.

Abstract: A memory circuit comprises a memory array having a plurality of memory cells arranged in rows and columns. Column select circuits enable access to the columns in the array. Each column select circuit is associated with a respective group of the columns and is arranged to access a selected one of the columns in the respective group. At least one spare memory column is provided. Also included are a plurality of read/write circuits associated respectively with the groups, and with the spare memory column, for reading or writing data bits between a data bus and the columns selected by the column selected circuits. Routing circuitry is connected between the read/write circuits and the data bus and is programmable with information identifying at least one faulty column.