Abstract: An e-Fuse device including a first electronic feature and a second electronic feature comprised of a conductive material, each of the first electronic feature and the second electronic feature having a width at least as great as a ground rule of a patterning process; and a fuse element comprised of the conductive material having a width less than the ground rule of the patterning process, the fuse element connecting a bottom portion of the first electronic feature and a bottom portion of the second electronic feature. Also disclosed is a method of making the e-Fuse device.

Abstract: An e-Fuse device including a first electronic feature and a second electronic feature comprised of a conductive material, each of the first electronic feature and the second electronic feature having a width at least as great as a ground rule of a patterning process; and a fuse element comprised of the conductive material having a width less than the ground rule of the patterning process, the fuse element connecting a bottom portion of the first electronic feature and a bottom portion of the second electronic feature. Also disclosed is a method of making the e-Fuse device.

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

Abstract: A three plate MIM capacitor structure includes a three plate MIM capacitor, a first wire in a metal layer above/below the three plate MIM, a second wire below/above the three plate MIM, a third wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first wire and the second and third wires or detecting leakage current across the second wire and the third wire.

Abstract: A three plate MIM capacitor test structure includes a three plate MIM capacitor, a first test wire in a metal layer above/below the three plate MIM, a second test wire below/above the three plate MIM, a third test wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first test wire and the second and third test wires or detecting leakage current across the second test wire and the third test wire.

Abstract: A three plate MIM capacitor test structure includes a three plate MIM capacitor, a first test wire in a metal layer above/below the three plate MIM, a second test wire below/above the three plate MIM, a third test wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first test wire and the second and third test wires or detecting leakage current across the second test wire and the third test wire.

Abstract: A three plate MIM capacitor structure includes a three plate MIM capacitor, a first wire in a metal layer above/below the three plate MIM, a second wire below/above the three plate MIM, a third wire below/above the three plate MIM, a first via connected to the first test wire, a second via connected to a middle plate of the three plate MIM, and a third via connected to the top and bottom plates of the three plate MIM. The test structure may verify the integrity the MIM capacitor by applying a potential to the first test wire, applying ground potential to both the second test wire and the third test wire, and detecting leakage current across the first wire and the second and third wires or detecting leakage current across the second wire and the third wire.

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Abstract: The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Abstract: Aspects of the present disclosure provide an integrated circuit (IC) test structure. An IC structure according to the present disclosure can include: a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level; a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.

Abstract: A structure including an Mx level including a first Mx metal, a second Mx metal, and a third Mx metal abutting and electrically connected in sequence with one another, the second Mx metal including graphene, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via, the via electrically connects the third Mx metal to the Mx+1 metal in a vertical orientation.

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a TSV, and methods of manufacturing the IC structure and the TSV. An IC structure according to embodiments of the present invention may include a through-semiconductor via (TSV) embedded within a substrate, the TSV having an axial end; and a metal cap contacting the axial end of the TSV, wherein the metal cap has a greater electrical resistivity than the TSV.