Patents by Inventor Andrew T. Lauritzen
Andrew T. Lauritzen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10896657Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.Type: GrantFiled: April 17, 2017Date of Patent: January 19, 2021Assignee: Intel CorporationInventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws, Devan Burke, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu
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Publication number: 20200402298Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 30, 2020Publication date: December 24, 2020Applicant: Intel CorporationInventors: Andrew T. Lauritzen, Altug Koker, Louis Feng, Tomasz Janczak, David M. Cimini, Karthik Vaidyanathan, Abhishek Venkatesh, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
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Patent number: 10853995Abstract: Systems, apparatuses and methods may provide for technology that computes, by a shader in a fixed-functionality hardware shader library, a physically based shading model for a type of material. Additionally, the shader may shade one or more surfaces associated with the type of material in accordance with the physically based shading model. In one example, two or more shaders in the shader library are dedicated to different types of materials.Type: GrantFiled: June 12, 2019Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini
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Publication number: 20200334200Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: May 7, 2020Publication date: October 22, 2020Applicant: Intel CorporationInventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
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Publication number: 20200334896Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.Type: ApplicationFiled: May 4, 2020Publication date: October 22, 2020Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp, Jonathan Kennedy, Abhishek R. Appu, Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Slawomir Grajewski, Gabor Liktor, David M. Cimini, Andrew T. Lauritzen, Travis T. Schluessler, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Kai Xiao, Ankur N. Shah, Altug Koker
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Patent number: 10706612Abstract: An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.Type: GrantFiled: April 1, 2017Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Andrew T. Lauritzen, Altug Koker, Louis Feng, Tomasz Janczak, David M. Cimini, Karthik Vaidyanathan, Abhishek Venkatesh, Murali Ramadoss, Michael Apodaca, Prasoonkumar Surti
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Publication number: 20200211150Abstract: Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.Type: ApplicationFiled: December 30, 2019Publication date: July 2, 2020Applicant: Intel CorporationInventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini
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Patent number: 10672366Abstract: Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.Type: GrantFiled: July 15, 2019Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Abhishek R. Appu
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Publication number: 20200160534Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.Type: ApplicationFiled: November 19, 2019Publication date: May 21, 2020Applicant: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, John G. Gierach, Gabor Liktor, Andrew T. Lauritzen
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Patent number: 10649956Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 1, 2017Date of Patent: May 12, 2020Assignee: INTEL CORPORATIONInventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
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Patent number: 10643374Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.Type: GrantFiled: April 24, 2017Date of Patent: May 5, 2020Assignee: Intel CorporationInventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer Kp, Jonathan Kennedy, Abhishek R. Appu, Jeffery S. Boles, Balaji Vembu, Michael Apodaca, Slawomir Grajewski, Gabor Liktor, David M. Cimini, Andrew T. Lauritzen, Travis T. Schluessler, Murali Ramadoss, Abhishek Venkatesh, Joydeep Ray, Kai Xiao, Ankur N. Shah, Altug Koker
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Publication number: 20200073810Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.Type: ApplicationFiled: September 10, 2019Publication date: March 5, 2020Inventors: Andrew T. Lauritzen, Gabor Liktor, Tomer Bar-On, Hugues Labbe, John G. Gierach, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Altug Koker
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Publication number: 20200051524Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.Type: ApplicationFiled: July 16, 2019Publication date: February 13, 2020Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Nikos Kaburlasos, Joydeep Ray, John H. Feit, Travis T. Schluessler, Jacek Kwiatkowski, Philip R. Laws, Devan Burke, Elmoustapha Ould-Ahmed-Vall, Abhishek R. Appu
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Publication number: 20200005734Abstract: Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.Type: ApplicationFiled: July 15, 2019Publication date: January 2, 2020Applicant: Intel CorporationInventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Abhishek R. Appu
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Publication number: 20200005526Abstract: Systems, apparatuses and methods may provide for technology that computes, by a shader in a fixed-functionality hardware shader library, a physically based shading model for a type of material. Additionally, the shader may shade one or more surfaces associated with the type of material in accordance with the physically based shading model. In one example, two or more shaders in the shader library are dedicated to different types of materials.Type: ApplicationFiled: June 12, 2019Publication date: January 2, 2020Inventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini
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Patent number: 10521876Abstract: Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.Type: GrantFiled: April 17, 2017Date of Patent: December 31, 2019Assignee: Intel CorporationInventors: Louis Feng, Altug Koker, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini
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Publication number: 20190371042Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.Type: ApplicationFiled: June 20, 2019Publication date: December 5, 2019Applicant: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Gabor Liktor, Andrew T. Lauritzen, John G. Gierach
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Patent number: 10489915Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.Type: GrantFiled: April 1, 2017Date of Patent: November 26, 2019Assignee: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, John G. Gierach, Gabor Liktor, Andrew T. Lauritzen
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Patent number: 10452552Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.Type: GrantFiled: April 17, 2017Date of Patent: October 22, 2019Assignee: Intel CorporationInventors: Andrew T. Lauritzen, Gabor Liktor, Tomer Bar-On, Hugues Labbe, John G. Gierach, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Altug Koker
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Patent number: 10395623Abstract: Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.Type: GrantFiled: April 1, 2017Date of Patent: August 27, 2019Assignee: Intel CorporationInventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Abhishek R. Appu