Abstract: Transient MLLT3 overexpression in culture may be used to expand human HSCs in vitro, and thereby improve the efficiency and safety of HSC transplantation.

Abstract: Guardian Art training tools including efficiently and functionally created low-cost apparatus manifested in a plurality of elastically deformable modular polyhedral members, with striking surfaces angled in ordinal planes and elastic deformation in tower structures made from the polyhedral members attached by Velcro® brand of attachments, inter alia.

Abstract: Transient MLLT3 overexpression in culture may be used to expand human HSCs in vitro, and thereby improve the efficiency and safety of HSC transplantation.

Abstract: A method and apparatus for processing a bi-directional dataflow are disclosed which permits the transparent movement of data from one processor to another via a shared memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device. The shared memory may comprise a plurality of banks of synchronous dynamic random access memory (SDRAM) devices, and may be used to store packet data in a network.

Abstract: An apparatus and method for interfacing a processor to one or more co-processors interface provides a dual ported memory to be used as a message passing buffer between the processor and the co-processors. Both the processor and co-processors can connect asynchronously to the dual ported memory. Control logic monitors activity by the processor to alert the co-processors of communications by the processor written to the memory and otherwise allows the processor and co-processors to think they are interfacing directly with one another.

Abstract: An apparatus and method for interfacing a processor to one or more co-processors provides a dual ported memory to be used as a message passing buffer between the processor and the co-processors. Both the processor and co-processors can connect asynchronously to the dual ported memory. Control logic monitors activity by the processor to alert the co-processors of communications by the processor written to the memory and otherwise allows the processor and co-processors to think they are interfacing directly with one another.

Abstract: An architecture for intercepting and processing packets from a network is disclosed. The architecture provides both stateful and stateless processing of packets in the bi-directional network flow. Further, stateless processing is provided by a parallel arrangement of network processors while stateful processing is provided by a serial arrangement of network processors. The architecture permits leveraging existing bi-directional devices to process packets in a uni-directional flow, thereby increasing the throughput of the device. The ability to share state among the stateless processor, among the stateful processors of each packet flow direction and between the stateless and stateful processors provides for dynamic adaptability and analysis of both historical and bi-directional packet activity.

Abstract: A method and apparatus for processing a bi-directional dataflow are disclosed which permits the transparent movement of data from one processor to another via a shared memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device. The shared memory may comprise a plurality of banks of synchronous dynamic random access memory (SDRAM) devices, and may be used to store packet data in a network.

Abstract: An apparatus and method for enhancing the infrastructure of a network such as the Internet is disclosed. A packet interceptor/processor apparatus is coupled with the network so as to be able to intercept and process packets flowing over the network. Further, the apparatus provides external connectivity to other devices that wish to intercept packets as well. The apparatus applies one or more rules to the intercepted packets which execute one or more functions on a dynamically specified portion of the packet and take one or more actions with the packets. The apparatus is capable of analyzing any portion of the packet including the header and payload. Actions include releasing the packet unmodified, deleting the packet, modifying the packet, logging/storing information about the packet or forwarding the packet to an external device for subsequent processing. Further, the rules may be dynamically modified by the external devices.

Abstract: A downlink frame processing system (200) includes a packet switch (608) routing self addressed uplink data (706) from an input port to an output port, a memory (804) coupled to the output port, and a downlink scheduler (802) coupled to the memory (804). The memory (804) includes storage for at least two downlink beam hop locations (302, 304). The downlink scheduler (802) processes from one of a plurality of segments at least one scheduling entry (1312) that includes, for example, a header field (1316) defining at least one of a payload and frame type (1404) for at least one of a payload and frame (1200) to be transmitted, and payload data pointers (1502, 1504, 1506) into the memory (804).

Abstract: An apparatus and method for interfacing a processor to one or more co-processors interface is disclosed. The apparatus provides a dual ported memory to be used as a message passing buffer between the processor and the co-processor. Both the processor and co-processors can interface asynchronously to the dual ported memory. Control logic monitors activity by the processor to alert the co-processors of communications by the processor written to the memory and otherwise allow the processor and co-processors to think they are interfacing directly with one another.

Abstract: An inter-processor communications interface is disclosed. The interface permits the transparent movement of data from one processor to another via a memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device.

Abstract: An architecture for intercepting and processing packets from a network is disclosed. The architecture provides both stateful and stateless processing of packets in the bi-directional network flow. Further, stateless processing is provided by a parallel arrangement of network processors while stateful processing is provided by a serial arrangement of network processors. The architecture permits leveraging existing bi-directional devices to process packets in a uni-directional flow, thereby increasing the throughput of the device. The ability to share state among the stateless processor, among the stateful processors of each packet flow direction and between the stateless and stateful processors provides for dynamic adaptability and analysis of both historical and bi-directional packet activity.

Abstract: An apparatus and method for enhancing the infrastructure of a network such as the Internet is disclosed. A packet interceptor/processor apparatus is coupled with the network so as to be able to intercept and process packets flowing over the network. Further, the apparatus provides external connectivity to other devices that wish to intercept packets as well. The apparatus applies one or more rules to the intercepted packets which execute one or more functions on a dynamically specified portion of the packet and take one or more actions with the packets. The apparatus is capable of analyzing any portion of the packet including the header and payload. Actions include releasing the packet unmodified, deleting the packet, modifying the packet, logging/storing information about the packet or forwarding the packet to an external device for subsequent processing. Further, the rules may be dynamically modified by the external devices.