Abstract: A vertical electrical fuse (eFuse) is provided that can be blown utilizing a relatively small current. The vertical eFuse is embedded in various dielectric material layers and includes a fuse link that is located between, and vertically connected to, first and second electrically conductive structures, the fuse link having a gouging feature at the bottom thereof.

Abstract: A method and structure to isolate BEOL MIM capacitors shorted or rendered highly leaky due to in process, or service induced defects, in a semiconductor chip are provided such that the rejection and loss of yield of otherwise good chips is minimized. In one embodiment, the method incorporates an isolation element such as, for example, a fuse, or a phase change material such as, a metal/insulation transition metal material, in series between the MIM capacitor and the active circuit. When a high current passes through the element due to the MIM capacitor being defective, the isolation element is rendered highly resistive or electrically open thereby disconnecting the defective capacitor or electrode plate from the active circuitry.

Abstract: A via and a method of fabricating a via in an integrated circuit involve forming a trench in dielectric material deposited above a first cap of a first metal level. The method includes patterning a collar from insulator material directly above the first cap, and etching through the first cap, within an area surrounded by the collar, to a first metal layer of the first metal level directly below the first cap. A liner is conformally deposited. The liner lines sidewalls of the collar. A metal conductor is deposited to form the via and a second metal layer of a second metal level.

Abstract: An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an “insulator-to/from metal transition (IMT)” liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.

Abstract: A method and structure to isolate BEOL MIM capacitors shorted or rendered highly leaky due to in process, or service induced defects, in a semiconductor chip are provided such that the rejection and loss of yield of otherwise good chips is minimized. In one embodiment, the method incorporates an isolation element such as, for example, a fuse, or a phase change material such as, a metal/insulation transition metal material, in series between the MIM capacitor and the active circuit. When a high current passes through the element due to the MIM capacitor being defective, the isolation element is rendered highly resistive or electrically open thereby disconnecting the defective capacitor or electrode plate from the active circuitry.

Abstract: An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an “insulator-to/from metal transition (IMT)” liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.

Abstract: An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an “insulator-to/from metal transition (IMT)” liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.

Abstract: Back end of the line precision resistors that allow for high currents and for configuration as an eFuse by embedding a single thin film high resistive metal material within a dielectric layer, wherein the resisters are coupled to sidewalls of adjacent metal interconnects are described. The resistors can be formed in the metal one (M1) dielectric layer and can be coupled to sidewalls of the M1 interconnects. Also described are processes for fabricating integrated circuits including the resistors and/or e-Fuses.

Abstract: A graded cap is formed upon an interconnect, such as a back end of line wire. The graded cap includes a microstructure that uniformly changes from a metal nearest the interconnect to a metal nitride most distal from the interconnect. The graded cap is formed by nitriding a metal cap that is formed upon the interconnect. During nitriding an exposed one or more perimeter portions of the metal cap become a metal nitride with a larger amount or concentration of Nitrogen while one or more inner portions of the metal cap nearest the interconnect may be maintained as the metal or become the metal nitride with a fewer amount or concentration of Nitrogen. The resulting graded cap includes a gradually or uniformly changing microstructure between the one or more inner portions and the one or more perimeter portions.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.

Abstract: A semiconductor device is provided. A unit wiring level of the semiconductor device includes; first and second wiring layers spaced apart from each other on a support layer, a large space formed adjacent to the first wiring layer and including a first air gap of predetermined width as measured from a sidewall of the first wiring layer, and a portion of a thermally degradable material layer formed on the support layer, small space formed between the first and second wiring layers, wherein the small space is smaller than the large space, and a second air gap at least partially fills the small space, and a porous insulating layer formed on the first and second air gaps.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Abstract: Methods of manufacturing a semiconductor device include forming an NMOS transistor on a semiconductor substrate, forming a first interlayer dielectric layer on the NMOS transistor, and dehydrogenating the first interlayer dielectric layer. Dehydrogenating the first interlayer dielectric layer may change a stress of the first interlayer dielectric layer. In particular, the first interlayer dielectric layer may have a tensile stress of 200 MPa or more after dehydrogenization. Semiconductor devices including dehydrogenated interlayer dielectric layers are also provided.

Abstract: A semiconductor device is provided. A unit wiring level of the semiconductor device includes; first and second wiring layers spaced apart from each other on a support layer, a large space formed adjacent to the first wiring layer and including a first air gap of predetermined width as measured from a sidewall of the first wiring layer, and a portion of a thermally degradable material layer formed on the support layer, small space formed between the first and second wiring layers, wherein the small space is smaller than the large space, and a second air gap at least partially fills the small space, and a porous insulating layer formed on the first and second air gaps.

Abstract: A semiconductor device is provided. A unit wiring level of the semiconductor device includes; first and second wiring layers spaced apart from each other on a support layer, a large space formed adjacent to the first wiring layer and including a first air gap of predetermined width as measured from a sidewall of the first wiring layer, and a portion of a thermally degradable material layer formed on the support layer, small space formed between the first and second wiring layers, wherein the small space is smaller than the large space, and a second air gap at least partially fills the small space, and a porous insulating layer formed on the first and second air gaps.