Abstract: A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of FREF. A second delay line (104, 150) also receives the reference clock at an input. A logic circuit (130, 134, . . . , 138, 140) combines signals from the delay line taps of the first delay line (108) with signals from the delay line taps of the second and/or first delay line (104, 150, 108) to produce a collection of clock pulses having a combined clock rate of FREF*2N. At least one of the delay lines can be locked to the reference clock using a delay locked loop. The clock pulses can be logically combined with a seed register (204) contents to produce a recursive sequence or with data for convolutional encoding, or with pilot data for correlation in a CDMA transceiver.

Abstract: A reconfigurable processor circuit (200) consistent with certain embodiments of the present invention has an array of configurable circuit blocks (208), wherein certain of the configurable circuit blocks (208) comprise one of configurable arithmetic logic units and clocked digital logic circuits. A control processor (218) configures a function of a plurality of the configurable circuit blocks. A memory (224) stores program instructions used by the control processor (218). A multiple frequency generator (230) receives a reference clock and synthesizes the plurality of clock signals therefrom, each clock signal being configured in frequency by the control processor (218). A timing control circuit (236) receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the timing control circuit (236) operates under control of the control processor (218).

Abstract: A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18, . . . , 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A circuit consistent with certain embodiments of the present invention has a source of N reference clock frequencies (230), where N is an integer greater than one. N frequency extender circuits (954) receive the N reference clock frequencies and generating N frequency extended output clock signals therefrom. A plurality of N seed slewers (958) produce N seed update values. A plurality of N seed registers (962) each receive one of the N seed update values and produce N seed masks therefrom. A plurality of N logic circuits (966) each receive one of the N seed masks and one of the N frequency extended output clock signals. Each of the N logic circuits (966) produce a pseudorandom sequence from the seed mask and the frequency extended output clock signal. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of FREF. A second delay line (104, 150) also receives the reference clock at an input. A logic circuit (130, 134, . . . , 138, 140) combines signals from the delay line taps of the first delay line (108) with signals from the delay line taps of the second and/or first delay line (104, 150, 108) to produce a collection of clock pulses having a combined clock rate of FREF*2N. At least one of the delay lines can be locked to the reference clock using a delay locked loop. The clock pulses can be logically combined with a seed register (204) contents to produce a recursive sequence or with data for convolutional encoding, or with pilot data for correlation in a CDMA transceiver.

Abstract: A reconfigurable processor circuit (200) consistent with certain embodiments of the present invention has an array of configurable circuit blocks (, wherein certain of the configurable circuit blocks comprise one of configurable arithmetic logic units and clocked digital logic circuits. A control processor (218) configures a function of a plurality of the configurable circuit blocks. A memory (224) stores program instructions used by the control processor (218). A multiple frequency generator (212) receives a reference clock and synthesizes the plurality of clock signals therefrom, each clock signal being configured in frequency by the control processor (218). A timing control circuit (236) receives the plurality of clock signals, allocates the plurality of clock signals of different frequency among the plurality of circuit blocks and routes the clock signals to the circuit blocks, wherein the timing control circuit (236) operates under control of the control processor (218).