Patents by Inventor Andrew Tse

Andrew Tse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7106081
    Abstract: A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: September 12, 2006
    Assignee: Verigy IPco
    Inventors: Romi Mayder, Todd Sholl, Nasser Ali Jafari, Andrew Tse, Randy L. Bailey
  • Publication number: 20060006896
    Abstract: A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.
    Type: Application
    Filed: July 8, 2004
    Publication date: January 12, 2006
    Inventors: Romi Mayder, Todd Sholl, Nasser Jafari, Andrew Tse, Randy Bailey
  • Patent number: 6570397
    Abstract: Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: May 27, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Romi Mayder, Noriyuki Sugihara, Andrew Tse, Randy L. Bailey
  • Publication number: 20030030453
    Abstract: Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time.
    Type: Application
    Filed: August 7, 2001
    Publication date: February 13, 2003
    Inventors: Romi Mayder, Noriyuki Sugihara, Andrew Tse, Randy L. Bailey