Patents by Inventor Andrew V. Anderson
Andrew V. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11944130Abstract: A vaporizer device includes various modular components. The vaporizer device includes a first subassembly. The first subassembly includes a cartridge connector that secures a vaporizer cartridge to the vaporizer device and includes at least two receptacle contacts that electrically communicate with the vaporizer cartridge. The vaporizer device includes a second subassembly. The second subassembly includes a skeleton defining a rigid tray that retains at least a power source. The vaporizer device also includes a third subassembly. The third subassembly includes a plurality of charging contacts that supply power to the power source, and an end cap that encloses an end of the vaporizer device.Type: GrantFiled: December 24, 2020Date of Patent: April 2, 2024Assignee: JUUL Labs, Inc.Inventors: Samuel C. Anderson, Wei-Ling Chang, Brandon Cheung, Steven Christensen, Joseph Chun, Joseph R. Fisher, Jr., Nicholas J. Hatton, Kevin Lomeli, James Monsees, Andrew L. Murphy, Claire O'Malley, John R. Pelochino, Hugh Pham, Vipul V. Rahane, Matthew J. Taschner, Val Valentine, Kenneth Wong
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Patent number: 11544093Abstract: Examples herein relate to checkpoint replication and copying of updated checkpoint data. For example, a memory controller coupled to a memory can receive a write request with an associated address to write or update checkpoint data and track updates to checkpoint data based on at least two levels of memory region sizes. A first level is associated with a larger memory region size than a memory region size associated with the second level. In some examples, the first level is a cache-line memory region size and the second level is a page memory region size. Updates to the checkpoint data can be tracked at the second level unless an update was previously tracked at the first level. Reduced amounts of updated checkpoint data can be transmitted during a checkpoint replication by using multiple region size trackers.Type: GrantFiled: September 27, 2019Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Zhe Wang, Andrew V. Anderson, Alaa R. Alameldeen, Andrew M. Rudoff
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Patent number: 11436161Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.Type: GrantFiled: November 18, 2019Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Ravi L. Sahita, Gilbert Neiger, Vedvyas Shanbhogue, David M. Durham, Andrew V. Anderson, David A. Koufaty, Asit K. Mallick, Arumugam Thiyagarajah, Barry E. Huntley, Deepak K. Gupta, Michael Lemay, Joseph F. Cihula, Baiju V. Patel
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Publication number: 20220027287Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Applicant: Intel CorporationInventors: Ravi L. SAHITA, Gilbert NEIGER, Vedvyas SHANBHOGUE, David M. DURHAM, Andrew V. ANDERSON, David A. KOUFATY, Asit K. MALLICK, Arumugam THIYAGARAJAH, Barry E. HUNTLEY, Deepak K. GUPTA, Michael LEMAY, Joseph F. CIHULA, Baiju V. PATEL
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Patent number: 11144479Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.Type: GrantFiled: November 18, 2019Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Ravi L. Sahita, Gilbert Neiger, Vedvyas Shanbhogue, David M. Durham, Andrew V. Anderson, David A. Koufaty, Asit K. Mallick, Arumugam Thiyagarajah, Barry E. Huntley, Deepak K. Gupta, Michael Lemay, Joseph F. Cihula, Baiju V. Patel
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Patent number: 11048588Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.Type: GrantFiled: February 11, 2020Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
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Publication number: 20200379917Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.Type: ApplicationFiled: June 12, 2020Publication date: December 3, 2020Inventors: Gilbert Neiger, Baiju V. Patel, Gur Hildesheim, Ron Rais, Andrew V. Anderson, Jason W. Brandt, David M. Durham, Barry E. Huntley, Raanan Sade, Ravi L. Sahita, Vedvyas Shanbhogue, Arumugam Thiyagarajah
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Patent number: 10747682Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.Type: GrantFiled: March 5, 2018Date of Patent: August 18, 2020Assignee: Intel CorporationInventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron Rust, Sebastian Schoenberg
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Publication number: 20200257609Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.Type: ApplicationFiled: February 11, 2020Publication date: August 13, 2020Applicant: Intel CorporationInventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
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Patent number: 10713177Abstract: A processing system includes a processing core to execute a virtual machine (VM) comprising a guest operating system (OS) and a memory management unit, communicatively coupled to the processing core, comprising a storage device to store an extended page table entry (EPTE) comprising a mapping from a guest physical address (GPA) associated with the guest OS to an identifier of a memory frame, a first plurality of access right flags associated with accessing the memory frame in a first page mode referenced by an attribute of a memory page identified by the GPA, and a second plurality of access right flags associated with accessing the memory frame in a second page mode referenced by the attribute of the memory page identified by the GPA.Type: GrantFiled: September 9, 2016Date of Patent: July 14, 2020Assignee: Intel CorporationInventors: Gilbert Neiger, Baiju V. Patel, Gur Hildesheim, Ron Rais, Andrew V. Anderson, Jason W. Brandt, David M. Durham, Barry E. Huntley, Raanan Sade, Ravi L. Sahita, Vedvyas Shanbhogue, Arumugam Thiyagarajah
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Publication number: 20200159673Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.Type: ApplicationFiled: November 18, 2019Publication date: May 21, 2020Applicant: Intel CorporationInventors: RAVI L. SAHITA, GILBERT NEIGER, VEDVYAS SHANBHOGUE, DAVID M. DURHAM, ANDREW V. ANDERSON, DAVID A. KOUFATY, ASIT K. MALLICK, ARUMUGAM THIYAGARAJAH, BARRY E. HUNTLEY, DEEPAK K. GUPTA, MICHAEL LEMAY, JOSEPH F. CIHULA, BAIJU V. PATEL
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Patent number: 10599455Abstract: Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a hardware processor including event circuit to recognize a virtualization event, and evaluation circuit to determine whether to transfer control of the apparatus from a child guest to a parent guest in response to the virtualization event, wherein the child guest and the parent guest each include a bit per virtualization event to indicate whether the parent guest is to gain control when the virtualization event occurs.Type: GrantFiled: May 14, 2018Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Dion Rodgers, Richard A. Uhlig, Lawrence O. Smith, Barry E. Huntley
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Patent number: 10599547Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.Type: GrantFiled: November 30, 2017Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
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Publication number: 20200042343Abstract: Examples herein relate to checkpoint replication and copying of updated checkpoint data. For example, a memory controller coupled to a memory can receive a write request with an associated address to write or update checkpoint data and track updates to checkpoint data based on at least two levels of memory region sizes. A first level is associated with a larger memory region size than a memory region size associated with the second level. In some examples, the first level is a cache-line memory region size and the second level is a page memory region size. Updates to the checkpoint data can be tracked at the second level unless an update was previously tracked at the first level. Reduced amounts of updated checkpoint data can be transmitted during a checkpoint replication by using multiple region size trackers.Type: ApplicationFiled: September 27, 2019Publication date: February 6, 2020Inventors: Zhe WANG, Andrew V. ANDERSON, Alaa R. ALAMELDEEN, Andrew M. RUDOFF
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Patent number: 10515023Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.Type: GrantFiled: April 1, 2016Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Ravi L. Sahita, Gilbert Neiger, Vedvyas Shanbhogue, David M. Durham, Andrew V. Anderson, David A. Koufaty, Asit K. Mallick, Arumugam Thiyagarajah, Barry E. Huntley, Deepak K. Gupta, Michael Lemay, Joseph F. Cihula, Baiju V. Patel
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Patent number: 10503664Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.Type: GrantFiled: June 7, 2016Date of Patent: December 10, 2019Assignee: INTEL CORPORATIONInventors: David M. Durham, Ravi L. Sahita, Gilbert Neiger, Vedvyas Shanbhogue, Andrew V. Anderson, Michael Lemay, Joseph F. Cihula, Arumugam Thiyagarajah, Asit K. Mallick, Barry E. Huntley, David A. Koufaty, Deepak K. Gupta, Baiju V. Patel
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Patent number: 10489309Abstract: A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a storage unit to store a page table entry including one or more identifiers of memory frames, a protection key, and an access mode bit indicating whether the one or more memory frames are accessible according to a user mode or according to a supervisor mode, a first permission register including a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the user mode, and a second permission register storing a plurality of fields, each field comprising a set of bits reflecting a set of memory access permissions under the supervisor mode.Type: GrantFiled: October 21, 2014Date of Patent: November 26, 2019Assignee: Intel CorporationInventors: David A. Koufaty, Gilbert Neiger, Rajesh M. Sankaran, Andrew V. Anderson, Subramanya R. Dulloor, Werner Haas, Joseph Nuzman
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Patent number: 10324863Abstract: Generally, this disclosure provides systems, methods and computer readable media for a protected memory view in a virtual machine (VM) environment enabling nested page table access by trusted guest software outside of VMX root mode. The system may include an editor module configured to provide access to a nested page table structure, by operating system (OS) kernel components and by user space applications within a guest of the VM, wherein the nested page table structure is associated with one of the protected memory views. The system may also include a page handling processor configured to secure that access by maintaining security information in the nested page table structure.Type: GrantFiled: June 24, 2013Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Michael Lemay, David M. Durham, Ravi L. Sahita, Andrew V. Anderson
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Publication number: 20190121751Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.Type: ApplicationFiled: September 18, 2018Publication date: April 25, 2019Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Lawrence Smith, III, Scott D. Rodgers
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Patent number: 10235301Abstract: Generally, this disclosure provides systems, methods and computer readable media for a page table edit controller configured to control access to guest page tables by virtual machine (VM) guest software through the manipulation of extended page tables. The system may include a translation look-aside buffer (TLB) to maintain a policy to lock one or more guest linear addresses (GLAs) to one or more allowable guest physical addresses (GPAs); a page walk processor to update the TLB based on the guest page tables; and a page table edit control (PTEC) module to: identify entries of the guest page tables that map GLAs associated with the policy to a first GPA; verify that the mapping conforms to the policy; and place the guest page table into one of a plurality of restricted accessibility states based on the verification, the restricted accessibility applied to the VM guests and to the page walk processor.Type: GrantFiled: July 17, 2017Date of Patent: March 19, 2019Assignee: INTEL CORPORATIONInventors: Michael Lemay, David M. Durham, Andrew V. Anderson, Gilbert Neiger, Ravi L. Sahita