Abstract: A dielectrically isolated temperature compensated pressure transducer including: a wafer including a deflectable diaphragm formed therein, the diaphragm being capable of deflecting in response to an applied pressure, and the diaphragm defining an active region surrounded by an inactive region of the wafer; a plurality of dielectrically isolated piezoresistive elements formed on the active region of the wafer and coupled together to form a Wheatstone bridge configuration so as to cooperatively provide an output signal in response to and indicative of an amount of deflection of the diaphragm, the plurality of piezoresistive elements being undesirably operative to introduce an undesirable error into the output according to exposure of the wafer to an environmental condition; and, a dielectrically isolated resistor formed on the inactive region of the wafer and electrically coupled in series to the plurality of piezoresistive elements so as to at least partially compensate for the undesirable error.

Abstract: A dielectrically isolated temperature compensated pressure transducer including: a wafer including a deflectable diaphragm formed therein, the diaphragm being capable of deflecting in response to an applied pressure, and the diaphragm defining an active region surrounded by an inactive region of the wafer; a plurality of dielectrically isolated piezoresistive elements formed on the active region of the wafer and coupled together to form a Wheatstone bridge configuration so as to cooperatively provide an output signal in response to and indicative of an amount of deflection of the diaphragm, the plurality of piezoresistive elements being undesirably operative to introduce an undesirable error into the output according to exposure of the wafer to an environmental condition; and, a dielectrically isolated resistor formed on the inactive region of the wafer and electrically coupled in series to the plurality of piezoresistive elements so as to at least partially compensate for the undesirable error.

Abstract: A method for fabricating a semiconductor device comprising fabricating a sacrificial wafer having a substrate wafer which includes a diffused layer and one or two epi layers. The sacrificial wafer is fusion bonded to a separately fabricated carrier/handle wafer having a layer of oxide on its surface, to form a composite wafer. Selective regions of the composite wafer are anodized and oxidized to form a plurality of wells separated from each other by a dielectric insulating layer. Next, N- epi regions above P+ epi regions are removed or alternatively, P+ diffused layers are removed from above an N- epi layer in selected regions. Finally, P- or N- single crystal silicon is grown back to the removed regions, depending on how the regions were removed. If N- single crystal is grown back to the removed regions, a high temperature drive-in is employed to finish the processing. The final structure contains N and P regions which are dielectrically isolated from each other and from the substrate.

Abstract: A method of fabricating a high pressure piezoresistive pressure transducer having a substantially linear pressure versus stress output over its full range of operation. The method involves bonding a carrier wafer having a dielectric isolating layer on one surface and a supporting member on the opposite surface, to a pattern wafer containing at least two single crystalline longitudinal piezoresistive sensing elements of a second conductivity. Both the pattern wafer and sections of the carrier wafer are etched leaving the piezoresistive sensing elements bonded directly to the dielectric isolating layer, and a diaphragm member having a deflecting portion and a non-deflecting portion. The diaphragm member is constructed to have an aspect ratio which is of the order of magnitude of one.

Abstract: A method of fabricating a high pressure piezoresistive pressure transducer having a substantially linear pressure versus stress output over its full range of operation. The method involves bonding a carrier wafer having a dielectric isolating layer on one surface and a supporting member on the opposite surface, to a pattern wafer containing at least two single crystalline longitudinal piezoresistive sensing elements of a second conductivity. Both the pattern wafer and sections of the carrier wafer are etched leaving the piezoresistive sensing elements bonded directly to the dielectric isolating layer, and a diaphragm member having a deflecting portion and a non-deflecting portion. The diaphragm member is constructed to have an aspect ratio which is of the order of magnitude of one.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising a carrier wafer and a silicon gate region disposed on the carrier wafer. A source region and a drain region made from 3C-silicon carbide are disposed on the carrier wafer above the gate region. A gate oxide, derived from silicon, separates the source and drain regions from the gate region. Laterally oriented oxide trenches separate and dielectrically isolate the MOSFET device from other devices on the carrier wafer. Further, the MOSFET device described above is manufactured in a method comprising the steps of providing a carrier wafer having an oxide layer formed on a surface thereof. A layer of silicon having a given level of conductivity is bonded to the oxide layer of the carrier wafer. Selected portions of the layer of silicon are oxidized to create a plurality of dielectrically isolated silicon islands, one of which forms a gate region.