Abstract: The modulator comprises a serial to parallel converter which separates alternate bits of a serial-binary data stream into I and Q bit streams that are stored in associated shift registers, a pair of ROMs that drive associated D/A converters, and a quadrature-phase modulator. Each bit of the I and Q bit streams has a duration of 2T, where T is the bit interval or period of a data bit. Each of the ROMs comprises blocks of memory that contain a plurality of digital words. The present and immediate past I and Q bits in the shift registers, and a baud clock signal of one-half the data signal rate, are applied to address inputs of the ROMs for selecting associated memory blocks in the 2 ROMs. A counter then clocks the ROMs for sequentially outputting the contents of the addressed memory blocks to the converters which produce analog voltages that phase modulate a carrier signal for moving a resultant signal vector with a constant envelope during each bit interval.