Patents by Inventor Andrew V. Hoar

Andrew V. Hoar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7123583
    Abstract: A method for performing rate policing and re-marking in a packet switched communications network that can be used to enforce and/or monitor Class of Services (CoS) contracts including terms for single or multiple classes of service. A switching system configured as an ingress node on the network includes a network switch and rate policing and re-marking logic. The switch receives a data packet transmitted on the network, extracts information from at least one header field of the packet including a CoS parameter, a primary flow ID established for the packet, and a packet byte count, and provides the extracted information to the rate policing/re-marking logic. Next, the rate policing/re-marking logic performs flow record and token bucket processing on the primary packet flow to determine whether the packets of the primary flow conform to the bandwidth requirements specified in the CoS contract.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: October 17, 2006
    Assignee: Ericsson AB
    Inventors: Andrew V. Hoar, Gregory S. Lauer, Robert J. Walsh, Walter C. Milliken, Todd A. Snide
  • Publication number: 20030133448
    Abstract: A packet-based protocol includes data flow control signals for efficient transmission of data on various interconnects, including high speed parallel and serial interconnects. The packet protocol also enables routing of data in large systems or across standard video and computing networks. The packet protocol is data independent and permits sharing of different types of video data over a common interconnect and system design. The packet protocol also offers a flexible method for routing data between devices. Command data also may be sent between devices using this protocol. Using this packet protocol, any data storage or data processing device also may operate as a switch and may implement data flow control over its input and output interconnects. Flow controlled data transfer may be implemented using this protocol in a manner that is independent of the transport medium of the interconnect.
    Type: Application
    Filed: April 3, 1998
    Publication date: July 17, 2003
    Inventors: CRAIG R. FRINK, ANDREW V. HOAR
  • Publication number: 20020097677
    Abstract: A method for performing rate policing and re-marking in a packet switched communications network that can be used to enforce and/or monitor Class of Services (CoS) contracts including terms for single or multiple classes of service. A switching system configured as an ingress node on the network includes a network switch and rate policing and re-marking logic. The switch receives a data packet transmitted on the network, extracts information from at least one header field of the packet including a CoS parameter, a primary flow ID established for the packet, and a packet byte count, and provides the extracted information to the rate policing/re-marking logic. Next, the rate policing/re-marking logic performs flow record and token bucket processing on the primary packet flow to determine whether the packets of the primary flow conform to the bandwidth requirements specified in the CoS contract.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 25, 2002
    Inventors: Andrew V. Hoar, Gregory S. Lauer, Robert J. Walsh, Walter C. Milliken, Todd A. Snide
  • Patent number: 5870109
    Abstract: A graphics system for storing and editing graphic images represented by digital data, includes a frame memory for storing pixel data representing graphic images including first and second graphic objects. The pixel data is stored at addresses, each being associated with one or more graphic fragment forming the first and second graphic objects. First and second addresses are respectively associated with those of the graphic fragments forming the first and second graphic objects. A memory controller controls writing and reading the pixel data to and from the frame memory. A fragment editor is provided to receive the pixel data read from the first address and modify the associated fragment with the received pixel data so as to form modified pixel data. An address detector detects the first address responsive to a request to read the pixel data from the first address and the second address responsive to a subsequent request to read pixel data from the second address.
    Type: Grant
    Filed: June 6, 1997
    Date of Patent: February 9, 1999
    Assignee: Digital Equipment Corporation
    Inventors: Joel J. McCormack, Christopher C. Gianos, Andrew V. Hoar, Larry D. Seiler, Norman P. Jouppi, James T. Claffey