Patents by Inventor Andrew W. Cross

Andrew W. Cross has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12093789
    Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: September 17, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew W. Cross, Christopher Chamberland, Jay M. Gambetta, Jared B. Hertzberg, Theodore J. Yoder, Guanyu Zhu
  • Patent number: 11983471
    Abstract: A repository is configured in a hybrid data processing environment comprising a classical computing system and a quantum computing system, to hold a plurality of quantum circuit components (QCC(s)). A degree of difficulty in simulating the received QCC in the classical computing system is transformed into a classical hardness score. A degree of difficulty in implementing the received QCC in the quantum computing system is transformed into a quantum hardness score. A first parameter in a metadata data structure associated with the received QCC is populated with the classical hardness score. A second parameter in the metadata data structure associated with the received QCC is populated with the quantum hardness score. The received QCC is transformed into a library element by at least augmenting the received QCC with the metadata data structure. The library element is added to the repository.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: May 14, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jay M. Gambetta, Andrew W. Cross, Ali Javadiabhari, Dmitri Maslov
  • Publication number: 20240152335
    Abstract: According to an embodiment of the present invention, a method, system, and computer program product for preparing a CZ state for use in magic state distillation. The embodiment may include initializing a code state across data qubits. The embodiment may include measuring a CZ operator of the codes state on at least one ancilla qubit proximal to the data qubits. The embodiment may include performing additional quantum operations with the CZ state based on the measurement of the at least one ancilla qubit.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 9, 2024
    Inventors: Benjamin James Brown, Andrew W. Cross, Riddhi Swaroop Gupta, Tomas Raphael Jochym-O'Connor, Theodore James Yoder
  • Patent number: 11880743
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: January 23, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sergey Bravyi, Andrew W. Cross, Shelly-Erika Garion, Dmitri Maslov
  • Patent number: 11803441
    Abstract: Techniques regarding calibrating one or more quantum decoder algorithms are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a correlation inversion decoder component that can calibrate a quantum decoder algorithm for decoding a quantum error-correcting code by estimating hyperedge probabilities of a decoding hypergraph that are consistent with a syndrome dataset.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: October 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Edward Hong Chen, Andrew W. Cross, Youngseok Kim, Neereja Sundaresan, Maika Takita, Antonio Corcoles-Gonzalez, Theodore James Yoder
  • Publication number: 20230205622
    Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
    Type: Application
    Filed: January 13, 2023
    Publication date: June 29, 2023
    Inventors: Andrew W. Cross, Christopher Chamberland, Jay M. Gambetta, Jared B. Hertzberg, Theodore J. Yoder, Guanyu Zhu
  • Publication number: 20230186128
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.
    Type: Application
    Filed: February 13, 2023
    Publication date: June 15, 2023
    Inventors: Sergey Bravyi, Andrew W. Cross, Shelly-Erika Garion, Dmitri Maslov
  • Patent number: 11645132
    Abstract: A method includes executing a calibration operation on a set of qubits, in a first iteration, to produce a set of parameters, a first subset of the set of parameters corresponding to a first qubit of the set of qubits, and a second subset of the set of parameters corresponding to a second qubit of the set of qubits. In an embodiment, the method includes selecting the first qubit, responsive to a parameter of the first subset meeting an acceptability criterion. In an embodiment, the method includes forming a quantum gate, responsive to a second parameter of the second subset failing to meet a second acceptability criterion, using the first qubit and a third qubit.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: May 9, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Javadiabhari, Jay M. Gambetta, Andrew W. Cross, David C. Mckay
  • Patent number: 11620563
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: April 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sergey Bravyi, Andrew W. Cross, Shelly-Erika Garion, Dmitri Maslov
  • Publication number: 20230094612
    Abstract: Techniques regarding calibrating one or more quantum decoder algorithms are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a correlation inversion decoder component that can calibrate a quantum decoder algorithm for decoding a quantum error-correcting code by estimating hyperedge probabilities of a decoding hypergraph that are consistent with a syndrome dataset.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Inventors: Edward Hong Chen, Andrew W. Cross, Youngseok Kim, Neereja Sundaresan, Maika Takita, Antonio Corcoles-Gonzalez, Theodore James Yoder
  • Patent number: 11556411
    Abstract: A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Andrew W. Cross, Christopher Chamberland, Jay M. Gambetta, Jared B. Hertzberg, Theodore J. Yoder, Guanyu Zhu
  • Patent number: 11455207
    Abstract: A method of error correction for a quantum computer includes identifying each of a plurality of physical qubits arranged in a lattice pattern over a surface in a quantum processor of the quantum computer as a one of a data qubit, an ancilla qubit or a flag qubit to define a plurality of data qubits, ancilla qubits and flag qubits. Each pair of interacting data qubits interact with a flag qubit and adjacent flag qubits both interact with a common ancilla qubit. The method further includes performing measurements of weight-four stabilizers, weight-two stabilizers, or both of a surface code formed using at least a sub-plurality of the plurality of physical qubits, or performing measurements of weight-four Bacon-Shor type gauge operators; and correcting fault-tolerantly quantum errors in one or more of the at least sub-plurality of physical qubits based on a measurement from at least one flag qubit.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 27, 2022
    Assignee: International Business Machines Corporation
    Inventors: Christopher Chamberland, Guanyu Zhu, Theodore James Yoder, Andrew W. Cross
  • Patent number: 11449783
    Abstract: Techniques regarding encoding a quantum circuit to a trivalent lattice scheme to identify flag qubit outcomes are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a graph component that can encode a quantum circuit to a trivalent lattice that maps an ancilla qubit to a plurality of data qubits via a plurality of flag qubits based on a connectivity scheme of the quantum circuit.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: September 20, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher Chamberland, Theodore James Yoder, Andrew W. Cross, Guanyu Zhu
  • Patent number: 11430831
    Abstract: A quantum system includes a qubit array comprising a plurality of qubits. A bus resonator is coupled between at least one pair of qubits in the qubit array. A switch is coupled between the at least one qubit pair of qubits.
    Type: Grant
    Filed: June 20, 2020
    Date of Patent: August 30, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patryk Gumann, Andrew W. Cross, Sean Hart, Jay Michael Gambetta
  • Publication number: 20220229956
    Abstract: A repository is configured in a hybrid data processing environment comprising a classical computing system and a quantum computing system, to hold a plurality of quantum circuit components (QCC(s)). A degree of difficulty in simulating the received QCC in the classical computing system is transformed into a classical hardness score. A degree of difficulty in implementing the received QCC in the quantum computing system is transformed into a quantum hardness score. A first parameter in a metadata data structure associated with the received QCC is populated with the classical hardness score. A second parameter in the metadata data structure associated with the received QCC is populated with the quantum hardness score. The received QCC is transformed into a library element by at least augmenting the received QCC with the metadata data structure. The library element is added to the repository.
    Type: Application
    Filed: April 7, 2022
    Publication date: July 21, 2022
    Applicant: International Business Machines Corporation
    Inventors: JAY M. GAMBETTA, Andrew W. Cross, Ali Javadiabhari, Dmitri Maslov
  • Publication number: 20220188112
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate logical Hadamard gate operation and gauge fixing in subsystem codes are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components can comprise a gauge fixing component that applies a gauge fixing operation to a subsystem code of an encoded qubit to generate a switched subsystem code. The computer executable components can further comprise a transverse component that applies a transversal Hadamard operation to the switched subsystem code to generate a rotated subsystem code.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Inventors: Guanyu Zhu, Andrew W. Cross
  • Patent number: 11314908
    Abstract: A repository is configured in a hybrid data processing environment comprising a classical computing system and a quantum computing system, to hold a plurality of quantum circuit components (QCC(s)). A degree of difficulty in simulating the received QCC in the classical computing system is transformed into a classical hardness score. A degree of difficulty in implementing the received QCC in the quantum computing system is transformed into a quantum hardness score. A first parameter in a metadata data structure associated with the received QCC is populated with the classical hardness score. A second parameter in the metadata data structure associated with the received QCC is populated with the quantum hardness score. The received QCC is transformed into a library element by at least augmenting the received QCC with the metadata data structure. The library element is added to the repository.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 26, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jay M. Gambetta, Andrew W. Cross, Ali Javadiabhari, Dmitri Maslov
  • Publication number: 20220050710
    Abstract: A compatibility is ascertained between a configuration of a quantum processor (q-processor) of a quantum cloud compute node (QCCN) in a quantum cloud environment (QCE) and an operation requested in a first instruction in a portion (q-portion) of a job submitted to the QCE, the QCE including the QCCN and a conventional compute node (CCN), the CCN including a conventional processor configured for binary computations. In response to the ascertaining, a quantum instruction (q-instruction) is constructed corresponding to the first instruction. The q-instruction is executed using the q-processor of the QCCN to produce a quantum output signal (q-signal). The q-signal is transformed into a corresponding quantum computing result (q-result). A final result is returned to a submitting system that submitted the job, wherein the final result comprises the q-result.
    Type: Application
    Filed: January 29, 2021
    Publication date: February 17, 2022
    Applicant: International Business Machines Corporation
    Inventors: Lev Samuel Bishop, ANDREW W. CROSS, Ismael Faro Sertage, Jay M. Gambetta
  • Publication number: 20220035978
    Abstract: Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.
    Type: Application
    Filed: October 19, 2021
    Publication date: February 3, 2022
    Inventors: Sergey Bravyi, Andrew W. Cross, Shelly-Erika Garion, Dmitri Maslov
  • Publication number: 20220027171
    Abstract: A method includes executing a calibration operation on a set of qubits, in a first iteration, to produce a set of parameters, a first subset of the set of parameters corresponding to a first qubit of the set of qubits, and a second subset of the set of parameters corresponding to a second qubit of the set of qubits. In an embodiment, the method includes selecting the first qubit, responsive to a parameter of the first subset meeting an acceptability criterion. In an embodiment, the method includes forming a quantum gate, responsive to a second parameter of the second subset failing to meet a second acceptability criterion, using the first qubit and a third qubit.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 27, 2022
    Applicant: International Business Machines Corporation
    Inventors: Ali Javadiabhari, Jay M. Gambetta, Andrew W. Cross, David C. Mckay