Patents by Inventor Andrew W. Ott
Andrew W. Ott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7790631Abstract: Methods and apparatuses to selectively deposit a dielectric on a self-assembled monolayer (“SAM”) adsorbed metal are described. A wafer includes a device having a first electrode. A first self-assembled monolayer is deposited on the wafer covering the first electrode. Next, a portion of the first self-assembled monolayer is removed to expose the first electrode. The first self-assembled monolayer includes a hydrophobic layer. Further, second self-assembled monolayer is deposited on the first electrode. The second self-assembled monolayer includes a hydrophilic layer. Next, an insulating layer is deposited on the second self-assembled monolayer. Further, self-aligned contacts to one or more second electrodes of the device are formed.Type: GrantFiled: November 21, 2006Date of Patent: September 7, 2010Assignee: Intel CorporationInventors: Ajay K. Sharma, Sean King, Dennis Hanken, Andrew W. Ott
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Publication number: 20080116481Abstract: Methods and apparatuses to selectively deposit a dielectric on a self-assembled monolayer (“SAM”) adsorbed metal are described. A wafer includes a device having a first electrode. A first self-assembled monolayer is deposited on the wafer covering the first electrode. Next, a portion of the first self-assembled monolayer is removed to expose the first electrode. The first self-assembled monolayer includes a hydrophobic layer. Further, second self-assembled monolayer is deposited on the first electrode. The second self-assembled monolayer includes a hydrophilic layer. Next, an insulating layer is deposited on the second self-assembled monolayer. Further, self-aligned contacts to one or more second electrodes of the device are formed.Type: ApplicationFiled: November 21, 2006Publication date: May 22, 2008Inventors: Ajay K. Sharma, Sean King, Dennis Hanken, Andrew W. Ott
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Patent number: 7199473Abstract: Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.Type: GrantFiled: January 3, 2005Date of Patent: April 3, 2007Assignee: Intel CorporationInventors: Sean W. King, Andrew W. Ott
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Patent number: 7169715Abstract: In one embodiment, the present invention includes introducing a conventional precursor and an organic precursor having an organic porogen into a vapor deposition apparatus; and forming a dielectric layer having the organic porogen on a substrate within the vapor deposition apparatus from the precursors. In certain embodiments, at least a portion of the organic porogen may be removed after subsequent processing, such as dual damascene processing.Type: GrantFiled: March 21, 2003Date of Patent: January 30, 2007Assignee: Intel CorporationInventors: Andrew W. Ott, Grant M. Kloster, Robert P. Meagley, Michael D. Goodner
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Patent number: 7138158Abstract: In one embodiment, the present invention includes introducing a precursor containing hydrocarbon substituents and optionally a second conventional or hydrocarbon-containing precursor into a vapor deposition apparatus; and forming a dielectric layer having the hydrocarbon substituents on a substrate within the vapor deposition apparatus from the precursor(s). In certain embodiments, at least a portion of the hydrocarbon substituents may be later removed from the dielectric layer to reduce density thereof.Type: GrantFiled: February 28, 2003Date of Patent: November 21, 2006Assignee: Intel CorporationInventors: Robert P. Meagley, Michael D. Goodner, Andrew W. Ott, Grant M. Kloster, Michael L. McSwiney, Bob E. Leet
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Patent number: 7135775Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.Type: GrantFiled: November 12, 2002Date of Patent: November 14, 2006Assignee: Intel CorporationInventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege
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Patent number: 6974772Abstract: Embodiments of the invention provide a device with a hard mask layer between first and second ILD layers. The hard mask layer may have a k value approximately equal to the first and/or second ILD layers.Type: GrantFiled: August 19, 2004Date of Patent: December 13, 2005Assignee: Intel CorporationInventors: Sean W. King, Andrew W. Ott
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Publication number: 20040185679Abstract: In one embodiment, the present invention includes introducing a conventional precursor and an organic precursor having an organic porogen into a vapor deposition apparatus; and forming a dielectric layer having the organic porogen on a substrate within the vapor deposition apparatus from the precursors. In certain embodiments, at least a portion of the organic porogen may be removed after subsequent processing, such as dual damascene processing.Type: ApplicationFiled: March 21, 2003Publication date: September 23, 2004Inventors: Andrew W. Ott, Grant M. Kloster, Robert P. Meagley, Michael D. Goodner
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Publication number: 20040170760Abstract: In one embodiment, the present invention includes introducing a precursor containing hydrocarbon substituents and optionally a second conventional or hydrocarbon-containing precursor into a vapor deposition apparatus; and forming a dielectric layer having the hydrocarbon substituents on a substrate within the vapor deposition apparatus from the precursor(s). In certain embodiments, at least a portion of the hydrocarbon substituents may be later removed from the dielectric layer to reduce density thereof.Type: ApplicationFiled: February 28, 2003Publication date: September 2, 2004Inventors: Robert P. Meagley, Michael D. Goodner, Andrew W. Ott, Grant M. Kloster, Michael L. McSwiney, Bob E. Leet
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Publication number: 20040119163Abstract: A method for making a semiconductor device using carbon nitride as an etch stop diffusion barrier and/or a hard mask is described. An interconnect structure is made by at least: forming an etch stop diffusion layer, depositing an interlayer dielectric, etching necessary vias and trenches, forming a barrier layer, forming copper alloy, and planarizing. The use of a hard mask in the method is optional. The etch stop diffusion layer, the optional hard mask, or both comprised by carbon nitride.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: Lawrence Wong, Jihperng Leu, Grant Kloster, Andrew W. Ott, Patrick Morrow
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Publication number: 20040101667Abstract: The present invention discloses a method including: determining whether a surface of a dielectric layer is reactive; activating the surface if the surface is not reactive; performing a cycle on the surface, the cycle including: reacting the surface with a metal; and activating the metal.Type: ApplicationFiled: November 6, 2003Publication date: May 27, 2004Inventors: Jennifer O'Loughlin, Andrew W. Ott, Bruce J. Tufts
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Patent number: 6713873Abstract: The present invention discloses a method including: determining whether a surface of a dielectric layer is reactive; activating the surface if the surface is not reactive; performing a cycle on the surface, the cycle including: reacting the surface with a metal; and activating the metal. The present invention also discloses a structure including: a substrate; a first interlayer dielectric located over the substrate; a first adhesion promoter layer located over the first interlayer dielectric; an etch stop layer located over the first adhesion promoter layer; a second adhesion promoter layer located over the etch stop layer; and a second interlayer dielectric located over the second adhesion promoter layer.Type: GrantFiled: November 27, 2002Date of Patent: March 30, 2004Assignee: Intel CorporationInventors: Jennifer O'Loughlin, Andrew W. Ott, Bruce J. Tufts
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Publication number: 20030137050Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.Type: ApplicationFiled: November 12, 2002Publication date: July 24, 2003Inventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege
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Patent number: 6518184Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.Type: GrantFiled: January 18, 2002Date of Patent: February 11, 2003Assignee: Intel CorporationInventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege
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Patent number: 6051517Abstract: A modified zeolite or molecular sieve membrane for separation of materials on a molecular scale. The modified membrane is fabricated to wholly or partially block regions between zeolite crystals to inhibit transfer of larger molecules through the membrane, but without blocking or substantially inhibiting transfer of small molecules through pores in the crystalline structure. The modified membrane has a monomolecular layer deposited on the zeolite surface which has coordinated groups of atoms that include (i) a metal atom bonded to oxygen atoms that are bonded to the zeolite substrate atoms (e.g., silicon atoms) and (ii) either hydroxyl groups bonded to the metal atoms or additional oxygen atoms bonded to the metal atoms.Type: GrantFiled: January 26, 1999Date of Patent: April 18, 2000Assignee: University Technology Corp.Inventors: Hans H. Funke, Jason W. Klaus, Steven M. George, Andrew W. Ott, John L. Falconer, Richard D. Noble
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Patent number: 6043177Abstract: A process for modifying surfaces of zeolites and molecular sieve membranes to decrease effective pore size for separation of materials includes atomic layer controlled vapor or liquid deposition. The atomic layer controlled deposition process steps include (i) exposing the surface to a metal atom coordinated with ligand groups having bonds that are hydrolyzable to form molecular bonded structures on the surface, which structures comprise the metal atoms coordinated with the ligand group or a modified ligand group and then (ii) hydrolyzing the bonds and possibly, but not necessarily, cross-linking the bonds in the ligand or modified ligand group.Type: GrantFiled: January 21, 1997Date of Patent: March 28, 2000Assignee: University Technology CorporationInventors: John L. Falconer, Steven M. George, Andrew W. Ott, Jason W. Klaus, Richard D. Noble, Hans H. Funke