Patents by Inventor Andrew W. Vogan

Andrew W. Vogan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11972143
    Abstract: Disclosed herein are techniques for balancing write commands directed to a non-volatile memory. According to some embodiments, a method may include caching a plurality of write commands into a write cache, and, in response to determining that an available capacity of the write cache satisfies a first threshold value: performing at least one write operation by directing data associated with the write commands in the write cache to the first partition of the non-volatile memory in response to determining that an available capacity of a first partition of the non-volatile memory satisfies a second threshold value; and performing at least one write operation by directing data associated with the write commands in the write cache to a second partition of the non-volatile memory in response to determining that the available capacity of the first partition of the non-volatile memory does not satisfy the second threshold value.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: April 30, 2024
    Assignee: Apple Inc.
    Inventors: Matthew J. Byom, Tudor Antoniu, Alexander Paley, Andrew W. Vogan, Muhammad N. Ashraf
  • Publication number: 20230142948
    Abstract: Disclosed herein are techniques for managing context information for data stored within a non-volatile memory of a computing device. According to some embodiments, the method can include (1) loading, into a volatile memory of the computing device, the context information from the non-volatile memory, where the context information is separated into a plurality of silos, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: (i) identifying a next silo of the plurality of silos to be written into the non-volatile memory, (ii) updating the next silo to reflect the transactions that apply to the next silo, and (iii) writing the next silo into the non-volatile memory. In turn, when an inadvertent shutdown of the computing device occurs, the silos of which the context information is comprised can be sequentially accessed and restored in an efficient manner.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 11, 2023
    Inventors: Alexander PALEY, Andrew W. VOGAN
  • Patent number: 11579789
    Abstract: Disclosed herein are techniques for managing context information for data stored within a non-volatile memory of a computing device. According to some embodiments, the method can include (1) loading, into a volatile memory of the computing device, the context information from the non-volatile memory, where the context information is separated into a plurality of silos, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: (i) identifying a next silo of the plurality of silos to be written into the non-volatile memory, (ii) updating the next silo to reflect the transactions that apply to the next silo, and (iii) writing the next silo into the non-volatile memory. In turn, when an inadvertent shutdown of the computing device occurs, the silos of which the context information is comprised can be sequentially accessed and restored in an efficient manner.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 14, 2023
    Assignee: Apple Inc.
    Inventors: Alexander Paley, Andrew W. Vogan
  • Patent number: 11544159
    Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: January 3, 2023
    Assignee: Apple Inc.
    Inventors: Alexander Paley, Andrew W. Vogan, Tudor Antoniu
  • Patent number: 11494107
    Abstract: Disclosed herein are techniques for managing parity information for data stored on a storage device. A method includes (1) receiving a request to store data into the storage device, (2) storing portions of the data in data pages included in stripes in a band of the storage device, where a respective data page is stored on a respective different die of a respective stripe, (3) determining primary parity information for a first stripe including a subset of the data pages, (4) storing the primary parity information in a primary parity page included in a second stripe in the stripes in the band, where the primary parity page is disposed on a next available die relative to dies storing the data pages, (5) determining secondary parity information for the second stripe, and (6) storing the secondary parity information in a secondary parity page included in the stripes in the band.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: November 8, 2022
    Assignee: Apple Inc.
    Inventors: Alexander Paley, Andrew W. Vogan, Evgeny Televitckiy
  • Publication number: 20220326877
    Abstract: Disclosed herein are techniques for balancing write commands directed to a non-volatile memory. According to some embodiments, a method may include caching a plurality of write commands into a write cache, and, in response to determining that an available capacity of the write cache satisfies a first threshold value: performing at least one write operation by directing data associated with the write commands in the write cache to the first partition of the non-volatile memory in response to determining that an available capacity of a first partition of the non-volatile memory satisfies a second threshold value; and performing at least one write operation by directing data associated with the write commands in the write cache to a second partition of the non-volatile memory in response to determining that the available capacity of the first partition of the non-volatile memory does not satisfy the second threshold value.
    Type: Application
    Filed: April 5, 2021
    Publication date: October 13, 2022
    Inventors: Matthew J. BYOM, Tudor ANTONIU, Alexander PALEY, Andrew W. VOGAN, Muhammad N. ASHRAF
  • Publication number: 20220147258
    Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Inventors: Alexander PALEY, Andrew W. VOGAN
  • Patent number: 11288184
    Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein define a native logical space to manage relatively high volume data write operations and define an artificially limited logical space to manage relatively low volume data write operations. The native logical space may include native logical bands that are mapped to a native number of physical blocks to enable high volume, high data transfer of data. The artificially limited logical space may include artificially limited logical bands that are mapped to an artificially limited number of available physical blocks. The artificially limited logical bands are better suited for low volume, low data transfer of data and do not unnecessarily tie up a native number of physical blocks.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: March 29, 2022
    Assignee: Apple Inc.
    Inventor: Andrew W. Vogan
  • Patent number: 11256436
    Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: February 22, 2022
    Assignee: Apple Inc.
    Inventors: Alexander Paley, Andrew W. Vogan
  • Patent number: 11132145
    Abstract: Disclosed herein are techniques for reducing write amplification when processing write commands directed to a non-volatile memory. According to some embodiments, the method can include the steps of (1) receiving a first plurality of write commands and a second plurality of write commands, where the first plurality of write commands and the second plurality of write commands are separated by a fence command (2) caching the first plurality of write commands, the second plurality of write commands, and the fence command, and (3) in accordance with the fence command, and in response to identifying that at least one condition is satisfied: (i) issuing the first plurality of write commands to the non-volatile memory, (ii) issuing the second plurality of write commands to the non-volatile memory, and (iii) updating log information to reflect that the first plurality of write commands precede the second plurality of write commands.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 28, 2021
    Assignee: Apple Inc.
    Inventors: Yuhua Liu, Andrew W. Vogan, Matthew J. Byom, Alexander Paley
  • Publication number: 20210224186
    Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein define a native logical space to manage relatively high volume data write operations and define an artificially limited logical space to manage relatively low volume data write operations. The native logical space may include native logical bands that are mapped to a native number of physical blocks to enable high volume, high data transfer of data. The artificially limited logical space may include artificially limited logical bands that are mapped to an artificially limited number of available physical blocks. The artificially limited logical bands are better suited for low volume, low data transfer of data and do not unnecessarily tie up a native number of physical blocks.
    Type: Application
    Filed: December 22, 2020
    Publication date: July 22, 2021
    Inventor: Andrew W. VOGAN
  • Patent number: 10977119
    Abstract: Disclosed are techniques for managing parity information for data stored on a storage device. A method can be implemented at a computing device communicably coupled to the storage device, and include (1) receiving a request to write data into a data band of the storage device, (2) writing the data into stripes of the data band, comprising, for each stripe of the data band: (i) calculating first parity information for the data written into the stripe, (ii) writing the first parity information into a volatile memory, and (iii) in response to determining that a threshold number of stripes have been written: converting the first parity information into smaller second parity information, and (3) in response to determining that the data band is read-verified: (i) converting the second parity information into smaller third parity information, and (ii) storing the smaller third parity information into a parity band of the storage device.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: April 13, 2021
    Assignee: Apple Inc.
    Inventors: Eran Roll, Stas Mouler, Matthew J. Byom, Andrew W. Vogan, Muhammad N. Ashraf, Elad Harush, Roman Guy
  • Publication number: 20210011819
    Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Inventors: Alexander PALEY, Andrew W. VOGAN, Tudor ANTONIU
  • Patent number: 10872035
    Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein define a native logical space to manage relatively high volume data write operations and define an artificially limited logical space to manage relatively low volume data write operations. The native logical space may include native logical bands that are mapped to a native number of physical blocks to enable high volume, high data transfer of data. The artificially limited logical space may include artificially limited logical bands that are mapped to an artificially limited number of available physical blocks. The artificially limited logical bands are better suited for low volume, low data transfer of data and do not unnecessarily tie up a native number of physical blocks.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 22, 2020
    Assignee: APPLE INC.
    Inventor: Andrew W. Vogan
  • Publication number: 20200379897
    Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein define a native logical space to manage relatively high volume data write operations and define an artificially limited logical space to manage relatively low volume data write operations. The native logical space may include native logical bands that are mapped to a native number of physical blocks to enable high volume, high data transfer of data. The artificially limited logical space may include artificially limited logical bands that are mapped to an artificially limited number of available physical blocks. The artificially limited logical bands are better suited for low volume, low data transfer of data and do not unnecessarily tie up a native number of physical blocks.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Inventor: Andrew W. Vogan
  • Patent number: 10853199
    Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 1, 2020
    Assignee: Apple Inc.
    Inventors: Alexander Paley, Andrew W. Vogan, Tudor Antoniu
  • Publication number: 20200326857
    Abstract: Disclosed herein are techniques for managing parity information for data stored on a storage device. A method includes (1) receiving a request to store data into the storage device, (2) storing portions of the data in data pages included in stripes in a band of the storage device, where a respective data page is stored on a respective different die of a respective stripe, (3) determining primary parity information for a first stripe including a subset of the data pages, (4) storing the primary parity information in a primary parity page included in a second stripe in the stripes in the band, where the primary parity page is disposed on a next available die relative to dies storing the data pages, (5) determining secondary parity information for the second stripe, and (6) storing the secondary parity information in a secondary parity page included in the stripes in the band.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 15, 2020
    Inventors: Alexander PALEY, Andrew W. VOGAN, Evgeny TELEVITCKIY
  • Publication number: 20200264792
    Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Alexander Paley, Andrew W. Vogan
  • Publication number: 20200104210
    Abstract: Disclosed are techniques for managing parity information for data stored on a storage device. A method can be implemented at a computing device communicably coupled to the storage device, and include (1) receiving a request to write data into a data band of the storage device, (2) writing the data into stripes of the data band, comprising, for each stripe of the data band: (i) calculating first parity information for the data written into the stripe, (ii) writing the first parity information into a volatile memory, and (iii) in response to determining that a threshold number of stripes have been written: converting the first parity information into smaller second parity information, and (3) in response to determining that the data band is read-verified: (i) converting the second parity information into smaller third parity information, and (ii) storing the smaller third parity information into a parity band of the storage device.
    Type: Application
    Filed: April 11, 2019
    Publication date: April 2, 2020
    Inventors: Eran ROLL, Stas MOULER, Matthew J. BYOM, Andrew W. VOGAN, Muhammad N. ASHRAF, Elad HARUSH, Roman GUY
  • Publication number: 20200089580
    Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Inventors: Alexander PALEY, Andrew W. VOGAN, Tudor ANTONIU