Patents by Inventor Andrew W. Welin

Andrew W. Welin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circular time differencing add/subtract delta to TMAX on sign, MSB
    Patent number: 9584432
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: February 28, 2017
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew W. Welin
  • SYSTEMS, PROCESSES AND INTEGRATED CIRCUITS FOR IMPROVED PACKET SCHEDULING OF MEDIA OVER PACKET
    Publication number: 20150341281
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 26, 2015
    Inventor: Andrew W. Welin
  • Producing silence packets in local buffer without sequencing, queuing, decoding
    Patent number: 9130876
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: September 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Andrew W. Welin
  • SYSTEMS, PROCESSES AND INTEGRATED CIRCUITS FOR IMPROVED PACKET SCHEDULING OF MEDIA OVER PACKET
    Publication number: 20130294441
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Application
    Filed: May 13, 2013
    Publication date: November 7, 2013
    Inventor: Andrew W. Welin
  • Processing unit decoding packets with deadlines in communications channel
    Patent number: 8503323
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: August 6, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew W. Welin
  • SYSTEMS, PROCESSES AND INTEGRATED CIRCUITS FOR IMPROVED PACKET SCHEDULING OF MEDIA OVER PACKET
    Publication number: 20110261719
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Application
    Filed: July 8, 2011
    Publication date: October 27, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Andrew W. Welin
  • Decoding packets with deadlines in communications channels processing unit
    Patent number: 8009688
    Abstract: A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: August 30, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Andrew W. Welin