Abstract: A detector for detecting the removal and/or insertion of a weapon out of and/or into a holster. The detector may transmit a message each time the weapon is removed from the holster. A recording system may receive the message and determine whether or not it will begin recording the data it captures. A detector may detect the change in a magnitude of an inductance and/or an impedance of a circuit to detect insertion and removal of the weapon into and out of the holster. The holster is configured to couple to the detector to position the detector to detect insertion and removal of the weapon. An adhesive tape may couple a detector to a holster.

Abstract: A computer system displays a representation of a field of view of the one or more cameras, including a representation of a portion of a three-dimensional physical environment that is in the field of view of the one or more cameras. The computer system receives a request to add a first virtual effect to the displayed representation of the field of view of the one or more cameras. In response to receiving the request to add the first virtual effect to the displayed representation of the field of view of the one or more cameras and in accordance with a determination that the first virtual effect requires a scan of the physical environment, the computer system initiates a scan of the physical environment to detect one or more features of the physical environment and displays a user interface that indicates a progress of the scan of the physical environment.

Abstract: Systems, methods, apparatuses, and computer-readable media for creating an observation video are described. The observation video may comprise a viewport that moves in coordination with motion of an HMD user's head and that shows portions of VR content being output to the HMD user at different times. For each of those times, motion data from the HMD may be used to determine a position, orientation, and/or shape of the viewport. The observation video may also include an element that represents the HMD user, which element may comprise a video element video isolated from video of the user captured by a camera, and/or which may comprise an animated avatar.

Abstract: Systems, methods, apparatuses, and computer-readable media for creating an observation video are described. The observation video may comprise a viewport that moves in coordination with motion of an HMD user's head and that shows portions of VR content being output to the HMD user at different times. For each of those times, motion data from the HMD may be used to determine a position, orientation, and/or shape of the viewport. The observation video may also include an element that represents the HMD user, which element may comprise a video element video isolated from video of the user captured by a camera, and/or which may comprise an animated avatar.

Abstract: In one of many embodiments, an InfiniBand network architecture is provided where a router circuitry communicates data between a host and a target device where the router circuitry includes circuitry for generating an external queue pair (QP) for establishing communication between the router circuitry and the host through a reliable connection (RC) session. The router circuitry also includes circuitry for generating internal queue pairs where the internal queue pairs establishes communication between the router circuitry and a device controller, between the between the device controller and the target device, and between the router circuitry and the target device by using reliable connection (RC) sessions. The router circuitry also includes mapping circuitry capable of establishing data destinations in communications between the target and the host. The internal queue pairs are coupled with the external queue pair through the mapping circuitry.

Abstract: A method for storing data is provided which includes transmitting a storage operation request to one of at least two controllers where the at least two controllers is capable of managing communication with a plurality of targets. The method further includes directing the storage operation request to an operational one of the at least two controllers when the one of the at least two controllers is inoperable. The method also includes processing the storage operation request with the operational one of the at least two controllers.

Abstract: A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.

Abstract: Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.

Abstract: Dual ported Input/Output (“I/O”) routers couple I/O devices to a cross-coupled switching fabric providing multiple levels of data path redundancy. Each I/O router possesses two or more internal ports allowing each I/O router to access multiple switches in a cross-coupled switching fabric. The additional redundant paths between each I/O device and each microprocessor complex provide additional means to balance data traffic and thereby maximize bandwidth utilization. I/O routers can be interleaved with single HBAs establishing access a switching fabric that uses cross-coupled nontransparent ports thus providing each I/O device with multiple paths upon which to pass data. Data paths are identified by a recursive address scheme that uniquely identifies each data path option available to each I/O device.

Abstract: A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.

Abstract: Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.

Abstract: A method for target device discovery on a network is disclosed. The method includes multicasting a signal from a master initiator over the network. A unicast is received from a new target recently connected to the network where the new target is passive when no multicast signal from the master initiator is received. Then the new target is added to a list of targets connected to the network. The method concludes by sending out a next multicast to other initiators where the next multicast includes information regarding the adding of the new target to the network.

Abstract: A network system for actively controlling congestion to optimize throughput is provided. The network system includes a sending host which is configured to send packet traffic at a set rate. The network system also includes a sending switch for receiving the packet traffic. The sending switch includes an input buffer for receiving the packet traffic at the set rate where the input buffer is actively monitored to ascertain a capacity level. The sending switch also includes code for setting a probability factor that is correlated to the capacity level where the probability factor increases as the capacity level increases and decreases as the capacity level decreases. The sending switch also has code for randomly generating a value where the value is indicative of whether packets being sent by the sending switch are to be marked with a congestion indicator.

Abstract: A method for processing storage data that is to be communicated over a network is provided. Initially, storage data to be transmitted over a network is provided. Once the data is provided, the method includes serializing the storage data using storage encapsulation protocol headers to generate serialized storage data. Then, the serialized storage data is encapsulated using a simple transport protocol to generate simple transport protocol data segments of the storage data. At this point, each of the simple transport protocol data segments are encapsulated into Ethernet frames. The Ethernet frames can then be communicated over standard Ethernet hubs and switches to enable communication to a selected storage target. In one example, the storage data is provided in the form of SCSI data, ATAPI data, and the like. This data can then be communicated to any storage target that may be connected to the network that is capable of processing the storage data.

Abstract: A method for optimizing data transmission in a data transfer system is provided where the data transfer system includes a transmitting device that transmits data to a receiving device through a switch. The method includes monitoring data transfer congestion in a buffer of the switch. The monitoring includes marking the data when data transfer congestion is detected. If data transfer congestion is detected, the method includes marking an acknowledgement (ACK) data after the marked data is received by the receiving device. The method further includes transmitting the ACK data from the receiving device to the transmitting device. The method also includes adjusting a data transfer rate between the transmitting device and the receiving device based on data transfer congestion. Monitoring data transfer congestion includes marking the data according to a probability corresponding to a percentage of time that the buffer is full.

Abstract: A method for processing data packets received at a computing system is provided. The method includes receiving a data packet and processing lower layer protocol headers of the data packet to expose overlying headers of the data packet. The overlying headers in a shared hardware component capable of executing header data for a transmission control protocol (TCP) communication and a storage transport protocol (STP) communication are processed. The header data for the TCP communication and the STP communication are positioned into standard header field locations. It is determined whether the data packet is from the TCP communication or the STP communication. If the data packet is from the TCP communication the processing of the overlying headers of the data packet separately in TCP processing is completed. If the data packet is from the STP communication, the processing of the overlying headers of the data packet separately in STP processing is completed.

Abstract: An Ethernet storage protocol (ESP) enabled network is provided. The network includes a host computer having host interface circuitry for communicating data in an Ethernet network, and the host interface circuitry is configured to receive parallel data from the host computer provided in accordance with a peripheral device protocol, serialize the parallel data, and encapsulate the serialized parallel data into Ethernet frames for transmission over the Ethernet network. The network also includes a target having target interface circuitry for communicating data in the Ethernet network. The target interface circuitry is configured to receive the encapsulated serialized parallel data and reconstruct the serialized parallel data into the peripheral device protocol. The peripheral device protocol is one of a SCSI protocol, an ATAPI protocol, and a UDMA protocol.

Abstract: A network stack layer interface is provided for efficient communication between network stack layers. The network stack layer interface includes a header portion that defines various characteristics of the network stack layer interface. In addition, a buffer descriptor is included that defines data that was, or will be, transmitted over the computer network. The buffer descriptor includes a memory address pointer to the data. In this manner, information is passed between network stack layers via the network stack interface, resulting in fast network data transfer with reduced data copying.

Abstract: Contention-based method and system are provided for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates the availability of data for transfer from a host adapter to a processor. The host adapter is coupled to one or more I/O devices over a bus. One or more I/O commands are received for transferring data between the processor and one or more I/O devices. Then, the contention for the bus among the I/O devices is monitored to determine how many devices are arbitrating for the bus.

Abstract: A network stack layer interface is provided for efficient communication between network stack layers. The network stack layer interface includes a header portion that defines various characteristics of the network stack layer interface. In addition, a buffer descriptor is included that defines data that was, or will be, transmitted over the computer network. The buffer descriptor includes a memory address pointer to the data. In this manner, information is passed between network stack layers via the network stack interface, resulting in fast network data transfer with reduced data copying.