Patents by Inventor Andrew Waterman

Andrew Waterman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210255859
    Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: Krste Asanovic, Andrew Waterman
  • Patent number: 11048515
    Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 29, 2021
    Assignee: SiFive, Inc.
    Inventors: Krste Asanovic, Andrew Waterman
  • Patent number: 10996952
    Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 4, 2021
    Assignee: SiFive, Inc.
    Inventors: Krste Asanovic, Andrew Waterman
  • Publication number: 20200210197
    Abstract: Systems and methods are disclosed for secure predictors for speculative execution. Some implementations may eliminate or mitigate side-channel attacks, such as the Spectre-class of attacks, in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions includes a predictor circuit that, when operating in a first mode, uses data stored in a set of predictor entries to generate predictions. For example, the integrated circuit may be configured to: detect a security domain transition for software being executed by the integrated circuit; responsive to the security domain transition, change a mode of the predictor circuit from the first mode to a second mode and invoke a reset of the set of predictor entries, wherein the second mode prevents the use of a first subset of the predictor entries of the set of predictor entries; and, after completion of the reset, change the mode back to the first mode.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 2, 2020
    Inventors: Krste Asanovic, Andrew Waterman
  • Publication number: 20200210189
    Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.
    Type: Application
    Filed: August 28, 2019
    Publication date: July 2, 2020
    Inventors: Krste Asanovic, Andrew Waterman
  • Publication number: 20200183687
    Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Inventors: Krste Asanovic, Andrew Waterman
  • Publication number: 20170017951
    Abstract: Processing of merchant-specific functionality services during proximity connection transactions. The merchant terminal transmits additional data to the computing device that enables the device to identify the merchant. The computing device can enable merchant-specific features, such as offers, rewards, loyalty information, and other incentives that are applicable to the identified merchant. The bi-directional communication between the devices permits the computing device to transmit these identified incentives to the merchant terminal. The merchant terminal can then adjust the purchase price. The computing device can also enable a merchant-specific financial instrument and can communicate the identity of the merchant to a management system.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 19, 2017
    Inventors: Johnie Lee, Roman Kalukiewicz, Titia Tin Yee Wong, Petra Cross, Andrew Waterman, Michael Kuo-Li Ying, Zachary Cancio
  • Publication number: 20170017940
    Abstract: Processing of merchant-specific functionality services during proximity connection transactions. The merchant terminal transmits additional data to the computing device that enables the device to identify the merchant. The computing device can enable merchant-specific features, such as offers, rewards, loyalty information, and other incentives that are applicable to the identified merchant. The bi-directional communication between the devices permits the computing device to transmit these identified incentives to the merchant terminal. The merchant terminal can then adjust the purchase price. The computing device can also enable a merchant-specific financial instrument and can communicate the identity of the merchant to a management system.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 19, 2017
    Inventors: Johnie Lee, Titia Tin Yee Wong, Andrew Waterman