Abstract: Embodiments herein describe an FFT that can bypass one or more stages when processing smaller frames. For example, when all the stages in the FFT are active, the FFT can process up to a maximum supported point size. However, the particular application may only every send smaller sized frames to the FFT. Instead of unnecessarily passing these frames through the beginning stages of the FFT (which adds latency and consumes power), the embodiments herein can bypass the unneeded stages which reduces the maximum point size the FFT can process but saves power and reduces latency. For example, the FFT can have selection circuitry (e.g., multiplexers) disposed between each stage that permits the input data to either bypass the previous stage(s) or the subsequent stage(s), depending on the architecture of the FFT. The bypassed stages can then be deactivated to conserve power.

Abstract: A method of controlling an LED string having a first end coupled to a power source and a second end coupled to a first end of a current sink is provided. The method include generating a target voltage at a first end of an external inductor coupled to the second end of the current sink, comparing the target voltage to a measured voltage at the first end of the external inductor, charging the external inductor responsive to the measured voltage being greater than the target voltage, and discharging the external inductor responsive to the measured voltage being less than the target voltage.

Abstract: An apparatus relating generally to accumulation is disclosed. In this apparatus, a first subtraction-bypass stage is coupled to receive an input operand and a modulus operand to provide a first difference and the input operand. An accumulation stage is coupled to the first subtraction-bypass stage to receive the first difference and the input operand. The accumulation stage is coupled to receive an offset operand for providing an offset-accumulated result. A second subtraction-bypass stage is coupled to receive the offset operand and the modulus operand to provide a second difference and the offset operand. A consolidation stage is coupled to receive the offset operand, the second difference and the offset-accumulated result to provide a consolidated accumulated result. The first subtraction-bypass stage, the accumulation stage, the second subtraction-bypass stage, and the consolidation stage are for a redundant number system.

Abstract: A method of controlling an LED string having a first end coupled to a power source and a second end coupled to a first end of a current sink is provided. The method include generating a target voltage at a first end of an external inductor coupled to the second end of the current sink, comparing the target voltage to a measured voltage at the first end of the external inductor, charging the external inductor responsive to the measured voltage being greater than the target voltage, and discharging the external inductor responsive to the measured voltage being less than the target voltage.

Abstract: An integrated circuit contains a current sink that is used to control a channel of varying forward voltage, with a goal of maintaining a minimally sufficient voltage across the current sink. A target voltage for the current sink return is determined, and a switched inductor is used to maintain said voltage. Various target determination schemes are possible, and various enhancements improve startup time, efficiency, and effectiveness.

Abstract: A circuit structure efficiently multiplies a first and second number. The circuit structure includes multipliers for the pairs of three-bit digits of the first number and three-bit digits of the second number. The multipliers produce six-bit partial products from the pair of three-bit digits of the first and second numbers. Each multiplier includes look-up tables receiving the pair of three-bit digits of the first and second numbers. A summing-tree circuit includes adders arranged in a series of levels, the adders in an initial one of the levels producing partial sums from the six-bit partial products from the multipliers, and for each first and successive second ones of the levels in the series, the adders in the second level producing another plurality of partial sums from the partial sums from the first level. A last one of the levels includes the adder that produces a product of the first and second numbers.

Abstract: An integrated circuit contains a current sink that is used to control a channel of varying forward voltage, with a goal of maintaining a minimally sufficient voltage across the current sink. A target voltage for the current sink return is determined, and a switched inductor is used to maintain said voltage. Various target determination schemes are possible, and various enhancements improve startup time, efficiency, and effectiveness.

Abstract: An efficient circuit and method for performing radix-3 Discrete Fourier transform (DFT) of a 3*2M size data frame are provided. The data frame is split and fast Fourier transform (FFT) processed as three sub-frames. Radix-3 operations are performed on the FFT processed sub-frames over a number of stages with time shared hardware to compute the DFT of the data-frame. FFT operations are performed on the second and third sub-frames to produce respective sub-transforms. Concurrently with FFT processing of the first sub-frame, butterfly operations are performed on the sub-transforms of the second and third sub-frames. Through the use of time-shared hardware and arranging FFT operations to correspond with radix-3 operations at various stages of processing, the DFT is performed with existing FFT processors while reducing resource requirements and/or reducing DFT transform time over the full-parallel radix-3 implementation.

Abstract: A multi-channel current regulator includes two or more channels, each channel acting as a current source or sink for a respective load. Each channel regulates its load current so that the load current is proportional to an input voltage supplied to the channel. An operational amplifier is shared between the channels. Each channel is selected in a rotating sequence for connection to the amplifier. As each channel is selected, a two-phase refresh cycle is initiated. During the first phase, the output of the amplifier is charged until it substantially matches the drive voltage of the selected channel. This is followed by the second phase where the output of the amplifier is adjusted until the load current of the selected channel is proportional to a set voltage Vset.

Abstract: A multi-channel current regulator includes two or more channels, each channel acting as a current source or sink for a respective load. Each channel regulates its load current so that the load current is proportional to an input voltage supplied to the channel. An operational amplifier is shared between the channels. Each channel is selected in a rotating sequence for connection to the amplifier. As each channel is selected, a two-phase refresh cycle is initiated. During the first phase, the output of the amplifier is charged until it substantially matches the drive voltage of the selected channel. This is followed by the second phase where the output of the amplifier is adjusted until the load current of the selected channel is proportional to a set voltage Vset.

Abstract: A multi-channel current regulator includes two or more channels, each channel acting as a current source or sink for a respective load. Each channel regulates its load current so that the load current is proportional to an input voltage supplied to the channel. An operational amplifier is shared between the channels. Each channel is selected in a rotating sequence for connection to the amplifier. As each channel is selected, a two-phase refresh cycle is initiated. During the first phase, the output of the amplifier is charged until it substantially matches the drive voltage of the selected channel. This is followed by the second phase where the output of the amplifier is adjusted until the load current of the selected channel is proportional to a set voltage Vset.

Abstract: Disclosed is an electrolytic cell utilizing an electrolyte circulation system designed to prevent buildup of sludge within the cell compartments and to insure a greater current efficiency by reason of the even distribution of electrolyte solution flow within the cell. This electrolytic cell is particularly suited for organic electrochemical production.