Abstract: In some embodiments of the invention, a device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer is disposed between the second semiconductor layer and the light emitting layer. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the third semiconductor layer is no more than 1%. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the second semiconductor layer is at least 1%. The third semiconductor layer is at least partially relaxed.

Abstract: In some embodiments of the invention, a device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer is disposed between the second semiconductor layer and the light emitting layer. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the third semiconductor layer is no more than 1%. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the second semiconductor layer is at least 1%. The third semiconductor layer is at least partially relaxed.

Abstract: In some embodiments of the invention, a device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer is disposed between the second semiconductor layer and the light emitting layer. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the third semiconductor layer is no more than 1%. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the second semiconductor layer is at least 1%. The third semiconductor layer is at least partially relaxed.

Abstract: A method according to embodiments of the invention includes providing an epitaxial structure comprising a donor layer and a strained layer. The epitaxial structure is treated to cause the strained layer to relax. Relaxation of the strained layer causes an in-plane lattice constant of the donor layer to change.

Abstract: A semiconductor structure comprises a III-nitride light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further comprises a curvature control layer grown on a first layer. The curvature control layer is disposed between the n-type region and the first layer. The curvature control layer has a theoretical a-lattice constant less than the theoretical a-lattice constant of GaN. The first layer is a substantially single crystal layer.

Abstract: A method according to embodiments of the invention includes providing an epitaxial structure comprising a donor layer and a strained layer. The epitaxial structure is treated to cause the strained layer to relax. Relaxation of the strained layer causes an in-plane lattice constant of the donor layer to change.

Abstract: In some embodiments of the invention, a device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region. The second semiconductor layer is disposed between the first semiconductor layer and the third semiconductor layer. The third semiconductor layer is disposed between the second semiconductor layer and the light emitting layer. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the third semiconductor layer is no more than 1%. A difference between the in-plane lattice constant of the first semiconductor layer and the bulk lattice constant of the second semiconductor layer is at least 1%. The third semiconductor layer is at least partially relaxed.

Abstract: A semiconductor structure comprises a III-nitride light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further comprises a curvature control layer grown on a first layer. The curvature control layer is disposed between the n-type region and the first layer. The curvature control layer has a theoretical a-lattice constant less than the theoretical a-lattice constant of GaN. The first layer is a substantially single crystal layer.

Abstract: A III-nitride light emitting device is grown on a textured substrate, in order to reduce the amount of total internal reflection at the interface between the substrate and the III-nitride layers. In some embodiments, the device includes a first growth region substantially free of voids, and a second growth region that improves the material quality such that high quality layers can be grown over the first and second regions.

Abstract: A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1−y)1−xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.

Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.

Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.

Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.

Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.

Abstract: A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1−y)1−xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.

Abstract: A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1-y)1-xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.