Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described.

Abstract: Thus, the present disclosure is directed to systems and methods for training neural networks using a tensor that includes a plurality of FP16 values and a plurality of bits that define an exponent shared by some or all of the FP16 values included in the tensor. The FP16 values may include IEEE 754 format 16-bit floating point values and the tensor may include a plurality of bits defining the shared exponent. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa and a variable bit-length exponent that may be dynamically set by processor circuitry. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa; a variable bit-length exponent that may be dynamically set by processor circuitry; and a shared exponent switch set by the processor circuitry to selectively combine the FP16 value exponent with the shared exponent.

Abstract: A network of matrix processing units (MPUs) is provided on a device, where each MPU is connected to at least one other MPU in the network, and each MPU is to perform matrix multiplication operations. Computer memory stores tensor data and a master control central processing unit (MCC) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. The MCC invokes a set of operations on one or more of the MPUs based on the instruction, where the set of operations includes operations on the tensor operands. A result is generated from the set of operations, the result embodied as a tensor value.

Abstract: Provided herein are methods for labeling the proteomes of cells, as well as methods for labeling proteins or populations of proteins produced by cells. In some embodiments, the methods comprise introducing variant aminoacyl-tRNA synthetases and noncanonical amino acids into cells. Also provided herein are polynucleotides encoding variant aminoacyl-tRNA synthetases that recognize noncanonical amino acids. The methods and compositions provided herein are useful for, among other things, identifying target cells and identifying biomarkers of interest.

Abstract: Thus, the present disclosure is directed to systems and methods for training neural networks using a tensor that includes a plurality of FP16 values and a plurality of bits that define an exponent shared by some or all of the FP16 values included in the tensor. The FP16 values may include IEEE 754 format 16-bit floating point values and the tensor may include a plurality of bits defining the shared exponent. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa and a variable bit-length exponent that may be dynamically set by processor circuitry. The tensor may include a shared exponent and FP16 values that include a variable bit-length mantissa; a variable bit-length exponent that may be dynamically set by processor circuitry; and a shared exponent switch set by the processor circuitry to selectively combine the FP16 value exponent with the shared exponent.

Abstract: A voltage regulating device and a mode switching detecting circuit are provided. The mode switching detecting circuit is configured to reset a soft start circuit of the voltage regulating device. The mode switching detecting circuit includes a mode switching signal detector, a reset signal generator, and a reset status detector. The mode switching signal detector receives a mode switching signal and generates a setting signal according to a transition edge of the mode switching signal. The reset signal generator is coupled to the mode switching signal detector and generates a reset activating signal according to the setting signal. The reset activating signal drives the soft start circuit to perform a reset operation. The reset status detector compares an output voltage of the soft start circuit and a reference voltage to generate a clear signal. The reset signal generator clears the reset activating signal according to the clear signal.

Abstract: Systems and methods for fast and efficient retrieval of NFT ownership information are provided. An exemplary method includes initializing a mirror blockchain by making a copy of an NFT blockchain; initializing an ownership transaction table and an NFT ledger from a mirror NFT blockchain by processing the mirror blockchain from a beginning block to an end block; periodically update the mirror blockchain with new blocks from an NFT blockchain thereby forming a new end block; processing ownership transaction events that modify NFT ownership in the new blocks up to a fixed offset from the new end block; updating the ownership transaction table; updating the NFT ledger; receiving a request for all NFTs owned by a crypto-wallet address; generating a response with the NFTs owned by the crypto-wallet address from the NFT ledger; selecting an NFT group; and verifying the NFT ledger against the NFT blockchain ownership.

Abstract: Systems and methods for providing high performance access to NFT metadata including ownership information. An example method requests NFT metadata from a server that has cached NFT metadata extracted from a mirror NFT blockchain. Periodically, new blocks that have been added to an NFT blockchain are added to the mirror blockchain and processed to update a cache with metadata modifications. Additionally, the method includes requests for NFT ownership information. An ownership transaction table is generated and updated from the mirror blockchain. Ownership request can include requests for all the NFTs owned by a crypto-wallet address.

Abstract: The disclosure provides a voltage regulator with a soft-start effect. The voltage regulator includes an amplifier, a first voltage setting circuit, a voltage selector and a power transistor. The amplifier has two input terminals to receive respectively a reference voltage and a feedback voltage. The amplifier has a current source to provide a current to an output terminal. In a voltage bypass mode, the first voltage setting circuit increases a driving voltage on the output terminal according to the current based on a selection voltage. In the voltage bypass mode, the voltage selector sequentially reduces the selection voltage respectively in multiple time intervals in a startup time interval. The power transistor receives the driving voltage, and generates an output voltage according to the driving voltage based on an operating power supply.

Abstract: A voltage regulator, including an amplifier, a voltage setting circuit and a power transistor, is provided. The amplifier includes a first current source and a second current source. The amplifier has two input terminals to respectively receive a reference voltage and a feedback voltage. The first current source is coupled between the operating power source and an output terminal of the amplifier, and provides a first current to the output terminal. The second current source is coupled between the output terminal and a reference ground terminal, and draws a second current from the output terminal. The voltage setting circuit is coupled to the output terminal, and increases a driving voltage on the output terminal according to the first current in a voltage bypass mode. The power transistor receives the driving voltage and generates an output voltage according to the driving voltage based on the operating power source.

Abstract: A network of matrix processing units (MPUs) is provided on a device, where each MPU is connected to at least one other MPU in the network, and each MPU is to perform matrix multiplication operations. Computer memory stores tensor data and a master control central processing unit (MCC) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. The MCC invokes a set of operations on one or more of the MPUs based on the instruction, where the set of operations includes operations on the tensor operands. A result is generated from the set of operations, the result embodied as a tensor value.

Abstract: Embodiments include an apparatus comprising an execution unit coupled to a memory, a microcode controller, and a hardware controller. The microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase, and use the first local hint to balance power consumption between the execution unit and the memory during parallel executions of the first and second instruction phases. The hardware controller is to use the global hint to determine an appropriate voltage level of a compute voltage and a frequency of a compute clock signal for the execution unit during the parallel executions of the first and second instruction phases. The first local hint includes a processing rate for the first instruction phase or an indication of the processing rate.

Abstract: Aspects of the present disclosure include methods, apparatuses, and computer readable media for receiving an indication of an asset of a manufacturer and a code associated with the asset, generating a token linked to a blockchain of the manufacturer, wherein the token includes a digital signature created using a creation key of the manufacturer, associating the token to the code of the asset, wherein the token remains locked until an indication is received, receiving the indication indicating the asset has passed a point of a supply chain and unlocking the token in response to receiving the indication.

Abstract: A network of matrix processing units (MPUs) is provided on a device, where each MPU is connected to at least one other MPU in the network, and each MPU is to perform matrix multiplication operations. Computer memory stores tensor data and a master control central processing unit (MCC) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. The MCC invokes a set of operations on one or more of the MPUs based on the instruction, where the set of operations includes operations on the tensor operands. A result is generated from the set of operations, the result embodied as a tensor value.

Abstract: The disclosure provides a voltage regulator with a soft-start effect. The voltage regulator includes an amplifier, a first voltage setting circuit, a voltage selector and a power transistor. The amplifier has two input terminals to receive respectively a reference voltage and a feedback voltage. The amplifier has a current source to provide a current to an output terminal. In a voltage bypass mode, the first voltage setting circuit increases a driving voltage on the output terminal according to the current based on a selection voltage. In the voltage bypass mode, the voltage selector sequentially reduces the selection voltage respectively in multiple time intervals in a startup time interval. The power transistor receives the driving voltage, and generates an output voltage according to the driving voltage based on an operating power supply.

Abstract: A voltage regulating device and a mode switching detecting circuit are provided. The mode switching detecting circuit is configured to reset a soft start circuit of the voltage regulating device. The mode switching detecting circuit includes a mode switching signal detector, a reset signal generator, and a reset status detector. The mode switching signal detector receives a mode switching signal and generates a setting signal according to a transition edge of the mode switching signal. The reset signal generator is coupled to the mode switching signal detector and generates a reset activating signal according to the setting signal. The reset activating signal drives the soft start circuit to perform a reset operation. The reset status detector compares an output voltage of the soft start circuit and a reference voltage to generate a clear signal. The reset signal generator clears the reset activating signal according to the clear signal.

Abstract: A voltage regulator, including an amplifier, a voltage setting circuit and a power transistor, is provided. The amplifier includes a first current source and a second current source. The amplifier has two input terminals to respectively receive a reference voltage and a feedback voltage. The first current source is coupled between the operating power source and an output terminal of the amplifier, and provides a first current to the output terminal. The second current source is coupled between the output terminal and a reference ground terminal, and draws a second current from the output terminal. The voltage setting circuit is coupled to the output terminal, and increases a driving voltage on the output terminal according to the first current in a voltage bypass mode. The power transistor receives the driving voltage and generates an output voltage according to the driving voltage based on the operating power source.

Abstract: Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.