Patents by Inventor Andrewe KUMMEL

Andrewe KUMMEL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12180583
    Abstract: A method of forming a conformal layer including TiN in a via includes introducing a precursor into a reaction chamber according to a first exposure schedule. The precursor includes non-halogenated metal-organic titanium. The first exposure schedule indicates precursor exposure periods. Each precursor exposure period is associated with a particular duration of time and a particular duty cycle over which to introduce the precursor during the particular duration of time. The method includes introducing a co-reactant into the reaction chamber according to a second exposure schedule. The co-reactant includes nitrogen. The second exposure schedule indicates co-reactant exposure periods. Each co-reactant exposure period is associated with a particular duration of time and a particular duty cycle over which to introduce the co-reactant during the particular duration of time. The method includes providing the conformal layer including TiN in the via based on said introducing the precursor and the co-reactant.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: December 31, 2024
    Assignees: The Regents of the University of California, Merck Patent GmbH
    Inventors: Andrew Kummel, Cheng-Hsuan Kuo, SeongUk Yun, Ravindra Kanjolia, Mansour Moinpour, Daniel Moser
  • Patent number: 12154787
    Abstract: Provided by the inventive concept are methods for fabricating semiconductor devices, such as methods of atomic layer deposition (ALD). Aspects of the inventive concept include methods for depositing and forming Ru metal layers having low resistivity, forming Ru metal layers without the need for a post-deposition annealing step, forming Ru metal layers selectively on portions of a substrate without the need for passivation, and providing Ru metal layers for use in back end of the line (BEOL) applications in semiconductor devices that do not require a liner/barrier layer.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: November 26, 2024
    Assignee: The Regents of the University of California
    Inventors: Michael Breeden, Victor Wang, Andrew Kummel
  • Publication number: 20240347502
    Abstract: Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventors: Mike Breeden, Victor Wang, Andrew Kummel, Ming-Jui Li, Muhannad Bakir, Jonathan Hollin, Nyi Myat Khine Linn, Charles H. Winter
  • Patent number: 12080549
    Abstract: A semiconductor structure includes a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al2O3 nanoparticles. The nanofog can also consists of sub 1 nm particles. Oxide layers can be formed on the nanofog, for example a bilayer stack of Al2O3—HfO2. Additional examples are from the group consisting of ZrO2, HfZrO2, silicon or other doped HfO2 or ZrO2, ZrTiO2, HfTiO2, La2O3, Y2O3, Ga2O3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO2, silicon or other doped HfO2 or ZrO2. The structure provides the basis for various devices, including MIM capacitors, FET transistors and MOSCAP capacitors.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: September 3, 2024
    Assignee: The Regents of the University of California
    Inventors: Iljo Kwak, Kasra Sardashti, Andrew Kummel
  • Patent number: 12027488
    Abstract: Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 2, 2024
    Assignees: The Regents of the University of California, Wayne State University, Georgia Tech Research Corporation
    Inventors: Mike Breeden, Victor Wang, Andrew Kummel, Ming-Jui Li, Muhannad Bakir, Jonathan Hollin, Nyi Myat Khine Linn, Charles H. Winter
  • Patent number: 11993844
    Abstract: The present inventive concept is related to methods for passivating an oxide layer and methods of selectively depositing a metal, metal nitride, metal oxide, or metal silicide layer on a metal, metal oxide, or silicide layer over an oxide layer including exposing the oxide layer to a passivant that selectively binds to the oxide layer over the metal, metal oxide, or silicide layer, and selectively growing the metal, metal nitride, metal oxide or metal silicide layer on the metal, metal oxide or silicide layer.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: May 28, 2024
    Assignee: The Regents of the University of California
    Inventors: Steven Wolf, Michael Breeden, Ashay Anurag, Andrew Kummel
  • Publication number: 20240052493
    Abstract: This invention allows for the deposition of aluminum nitride buffer layers and templating films that greatly enhance the quality of additional aluminum nitride deposited by alternate deposit ion techniques and reduce the overall thickness of needed buffer layers. Furthermore, these films can be deposited at substrate temperatures of 400° C. and 580° C. which is considerably lower than other techniques, such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD).
    Type: Application
    Filed: May 2, 2023
    Publication date: February 15, 2024
    Inventors: Aaron McLeod, Scott Ueda, Andrew Kummel
  • Publication number: 20230175133
    Abstract: Described are low resistivity metal layers/films, such as low resistivity ruthenium (Ru) layers/films, and methods of forming low resistivity metal films. Ru layers/films with close-to-bulk resistivity can be prepared on substrates using Ru(CpEt)2 + O2 ALD, as well as a two-step ALD process using Ru(DMBD)(CO)3 + TBA (tertiary butyl amine) to nucleate the substrate and Ru(EtCp)2 + O2 to increase layer/film thickness. The Ru layer/films and methods of preparing Ru layers/films described herein may be suitable for use in barrierless via-fills, as well as at M0/M1 interconnect layers.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 8, 2023
    Inventors: Andrew Kummel, Michael Breeden, Victor Wang, Ravindra Kanjolia, Mansour Moinpour, Harsono Simka
  • Publication number: 20230175118
    Abstract: A method of forming a conformal layer including TiN in a via includes introducing a precursor into a reaction chamber according to a first exposure schedule. The precursor includes non-halogenated metal-organic titanium. The first exposure schedule indicates precursor exposure periods. Each precursor exposure period is associated with a particular duration of time and a particular duty cycle over which to introduce the precursor during the particular duration of time. The method includes introducing a co-reactant into the reaction chamber according to a second exposure schedule. The co-reactant includes nitrogen. The second exposure schedule indicates co-reactant exposure periods. Each co-reactant exposure period is associated with a particular duration of time and a particular duty cycle over which to introduce the co-reactant during the particular duration of time. The method includes providing the conformal layer including TiN in the via based on said introducing the precursor and the co-reactant.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 8, 2023
    Inventors: Andrew Kummel, Cheng-Hsuan Kuo, SeongUk Yun, Ravindra Kanjolia, Mansour Moinpour, Daniel Moser
  • Patent number: 11532355
    Abstract: An N-bit non-volatile multi-level memory cell (MLC) can include a lower electrode and an upper electrode spaced above the lower electrode. N ferroelectric material layers can be vertically spaced apart from one another between the lower electrode and the upper electrode, wherein N is at least 2 and at least one dielectric material layer having a thickness of less than 20 nm can be located between the N ferroelectric material layers.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 20, 2022
    Assignees: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, UNIVERSITY OF NOTRE DAME DU LAC
    Inventors: Kai Ni, Suman Datta, Andrew Kummel
  • Publication number: 20220319830
    Abstract: A semiconductor structure includes a nanofog oxide adhered to an inert 2D or 3D surface or a weakly reactive metal surface, the nanofog oxide consisting essentially of 0.5-2 nm Al2O3 nanoparticles. The nanofog can also consists of sub 1 nm particles. Oxide layers can be formed on the nanofog, for example a bilayer stack of Al2O3—HfO2. Additional examples are from the group consisting of ZrO2, HfZrO2, silicon or other doped HfO2 or ZrO2, ZrTiO2, HfTiO2, La2O3, Y2O3, Ga2O3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO2, silicon or other doped HfO2 or ZrO2. The structure provides the basis for various devices, including MIM capacitors, FET transistors and MOSCAP capacitors.
    Type: Application
    Filed: August 9, 2021
    Publication date: October 6, 2022
    Inventors: Iljo Kwak, Kasra Sardashti, Andrew Kummel
  • Publication number: 20220189763
    Abstract: Provided by the inventive concept are methods for fabricating semiconductor devices, such as methods of atomic layer deposition (ALD). Aspects of the inventive concept include methods for depositing and forming Ru metal layers having low resistivity, forming Ru metal layers without the need for a post-deposition annealing step, forming Ru metal layers selectively on portions of a substrate without the need for passivation, and providing Ru metal layers for use in back end of the line (BEOL) applications in semiconductor devices that do not require a liner/barrier layer.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 16, 2022
    Inventors: Michael Breeden, Victor Wang, Andrew Kummel
  • Publication number: 20220077104
    Abstract: Methods of bonding and structures with such bonding are disclosed. One such method includes providing a first substrate with a first electrical contact; providing a second substrate with a second electrical contact above the first electrical contact, wherein an upper surface of the first electrical contact is spaced apart from a lower surface of the second electrical contact by a gap; and depositing a layer of selective metal on the lower surface of the second electrical contact and on the upper surface of the first electrical contact by a thermal Atomic Layer Deposition (ALD) process until the gap is filled to create a bond between the first electrical contact and the second electrical contact.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 10, 2022
    Inventors: Mike Breeden, Victor Wang, Andrew Kummel, Ming-Jui Li, Muhannad Bakir, Jonathan Hollin, Nyi Myat Khine Linn, Charles H. Winter
  • Publication number: 20210398848
    Abstract: The present inventive concept relates to selective metal layer deposition. Embodiments include a method for atomic layer deposition (ALD) of a metal, the method comprising at least one cycle of: a) exposing a substrate, the substrate comprising a surface comprising a metal portion and an insulator portion, to a metal-organic precursor; b) depositing a metal-organic precursor on an upper surface of the metal portion of the substrate to selectively provide a metal precursor layer on the upper surface of the metal portion of the substrate; c) exposing the metal precursor layer to a co-reactant; and d) depositing the co-reactant on the metal precursor layer, wherein the co-reactant takes part in a ligand exchange with the metal precursor layer.
    Type: Application
    Filed: December 3, 2019
    Publication date: December 23, 2021
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Ravindra KANJOLIA, Mansour MOINPOUR, Jacob WOODRUFF, Steven WOLF, Michael BREEDEN, Scott T. UEDA, Andrew KUMMEL, Ashay ANURAG
  • Patent number: 11127590
    Abstract: A method for forming a high-k oxide includes forming a nanofog of Al2O3 nanoparticles and conducting subsequent ALD deposition of a dielectric on the nanofog. A nanofog oxide is adhered to an inert 2D or 3D surface, the nano oxide consisting essentially of sub 1 nm Al2O3 nanoparticles. Additional oxide layers can be formed on the nanofog. Examples are from the group of selected from the group consisting of ZrO2, HfZrO2, silicon or other doped HfO2 or ZrO2, ZrTiO2, HfTiO2, La2O3, Y2O3, Ga2O3, GdGaOx, and alloys thereof, including the ferroelectric phases of HfZrO2, silicon or other doped HfO2 or ZrO2.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: September 21, 2021
    Assignee: The Regents of the University of California
    Inventors: Iljo Kwak, Kasra Sardashti, Andrew Kummel
  • Publication number: 20210249331
    Abstract: Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.
    Type: Application
    Filed: February 8, 2021
    Publication date: August 12, 2021
    Inventors: Scott Ueda, Aaron McLeod, Andrew Kummel, Mike Burkland, Eduardo M. Chumbes, Thomas E. Kazior, Eric Pop, Michelle Chen, Chris Perez, Mark Rodwell
  • Publication number: 20210098060
    Abstract: An N-bit non-volatile multi-level memory cell (MLC) can include a lower electrode and an upper electrode spaced above the lower electrode. N ferroelectric material layers can be vertically spaced apart from one another between the lower electrode and the upper electrode, wherein N is at least 2 and at least one dielectric material layer having a thickness of less than 20 nm can be located between the N ferroelectric material layers.
    Type: Application
    Filed: September 25, 2020
    Publication date: April 1, 2021
    Inventors: Kai Ni, Suman Datta, Andrew Kummel
  • Publication number: 20210038742
    Abstract: A composition comprising silica shells conjugated to a TLR7 agonist and methods of using the composition are provided.
    Type: Application
    Filed: June 19, 2020
    Publication date: February 11, 2021
    Inventors: Ching-Hsin Huang, Natalie Mendez, James Wang, Tomoko Hayashi, Joi Weeks, Oscar Hernandez Echeagaray, Andrew Kummel, William C. Trogler, Natalie A. Gude
  • Patent number: 10840350
    Abstract: The present disclosure provides a method of forming a nanolaminate structure. First, a pre-treatment is performed on a semiconductor substrate, in which the semiconductor substrate includes SiGe. Then, a first metal oxide layer is formed on the semiconductor substrate. Then, at least one second metal oxide layer and at least one third metal oxide layer are alternately stacked on the first metal oxide layer, thereby forming a nanolaminate structure. And, a conductive gate layer is formed on the nanolaminate structure.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 17, 2020
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Zi-Wei Fang, Hong-Fa Luan, Wilman Tsai, Kasra Sardashti, Maximillian Clemons, Scott Ueda, Mahmut Kavrik, Iljo Kwak, Andrew Kummel, Hsiang-Pi Chang
  • Publication number: 20200340112
    Abstract: The present inventive concept is related to methods for passivating an oxide layer and methods of selectively depositing a metal, metal nitride, metal oxide, or metal silicide layer on a metal, metal oxide, or silicide layer over an oxide layer including exposing the oxide layer to a passivant that selectively binds to the oxide layer over the metal, metal oxide, or silicide layer, and selectively growing the metal, metal nitride, metal oxide or metal silicide layer on the metal, metal oxide or silicide layer.
    Type: Application
    Filed: April 24, 2020
    Publication date: October 29, 2020
    Inventors: Steven Wolf, Michael Breeden, Ashay Anurag, Andrew Kummel