Patents by Inventor Andrey Chilikin
Andrey Chilikin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240334245Abstract: Examples described herein relate to a network interface device that performs: offloading processing of fragments of a packet to an accelerator; processing non-fragmented packets; and prioritizing dropping of fragments of the packet over dropping of non-fragmented packets. Offloading processing of fragments of the packet to the accelerator can include: the accelerator performing: reassembling the fragments of the packet into a first reassembly packet; and based on congestion associated with at least one of the fragments of the packet of the first reassembly packet: dropping fragments of the first reassembly packet associated with one or more flows; halting reassembly of the first reassembly packet; and forwarding a second packet to a host system, wherein the second packet indicates that congestion occurred, identifies one or more impacted flows, and indicates a number of dropped packet fragments.Type: ApplicationFiled: June 7, 2024Publication date: October 3, 2024Inventors: John J. BROWNE, Andrey CHILIKIN, Elazar COHEN, Joseph HASTING, James CLEE, Jerry PIROG, Jamison D. WHITESELL, Ambalavanar ARULAMBALAM, Anjali Singhai JAIN, Andrew CUNNINGHAM, Ruben DAHAN
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Patent number: 12093746Abstract: Technologies for the hierarchical clustering of hardware resources in network function virtualization (NFV) deployments include a compute node that is configured to create a network function profile that includes a plurality of network functions to be deployed on the compute node. Additionally, the compute node is configured to translate the network function profile usable to identify which of the plurality of network functions are to be managed by each of the plurality of interconnected hardware resources into a hardware profile for each of a plurality of interconnected hardware resources. The compute node is further configured to deploy each of the plurality of network functions to one or more of the plurality of interconnected hardware resources based on the hardware profile. Other embodiments are described herein.Type: GrantFiled: May 9, 2023Date of Patent: September 17, 2024Assignee: Intel CorporationInventors: Andrey Chilikin, Sugesh Chandran
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Patent number: 12067427Abstract: Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.Type: GrantFiled: July 19, 2022Date of Patent: August 20, 2024Assignee: Intel CorporationInventors: Eliezer Tamir, Johannes Berg, Andrew Cunningham, Peter Waskiewicz, Jr., Andrey Chilikin
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Patent number: 12026116Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.Type: GrantFiled: December 26, 2020Date of Patent: July 2, 2024Assignee: Intel CorporationInventors: Patrick G. Kutch, Andrey Chilikin, Niall D. McDonnell, Brian A. Keating, Naveen Lakkakula, Ilango S. Ganga, Venkidesh Krishna Iyer, Patrick Fleming, Lokpraveen Mosur
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Patent number: 11983131Abstract: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.Type: GrantFiled: December 26, 2020Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Patrick G. Kutch, Andrey Chilikin, Niall D. McDonnell, Brian A. Keating, Naveen Lakkakula, Ilango S. Ganga, Venkidesh Krishna Iyer, Patrick Fleming, Lokpraveen Mosur
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Patent number: 11934330Abstract: Examples described herein relate to an offload processor to receive data for transmission using a network interface or received in a packet by a network interface. In some examples, the offload processor can include a packet storage controller to determine whether to store data in a buffer of the offload processing device or a system memory after processing by the offload processing device. In some examples, determine whether to store data in a buffer of the offload processor or a system memory is based on one or more of: available buffer space, latency limit associated with the data, priority associated with the data, or available bandwidth through an interface between the buffer and the system memory. In some examples, the offload processor is to receive a descriptor and specify a storage location of data in the descriptor, wherein the storage location is within the buffer or the system memory.Type: GrantFiled: May 13, 2020Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Patrick G. Kutch, Andrey Chilikin
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Publication number: 20240089206Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Patrick CONNOR, Andrey CHILIKIN, Brendan RYAN, Chris MACNAMARA, John J. BROWNE, Krishnamurthy JAMBUR SATHYANARAYANA, Stephen DOYLE, Tomasz KANTECKI, Anthony KELLY, Ciara LOFTUS, Fiona TRAHE
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Patent number: 11855897Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.Type: GrantFiled: June 23, 2021Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Patrick Connor, Andrey Chilikin, Brendan Ryan, Chris MacNamara, John J. Browne, Krishnamurthy Jambur Sathyanarayana, Stephen Doyle, Tomasz Kantecki, Anthony Kelly, Ciara Loftus, Fiona Trahe
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Publication number: 20230359510Abstract: Technologies for the hierarchical clustering of hardware resources in network function virtualization (NFV) deployments include a compute node that is configured to create a network function profile that includes a plurality of network functions to be deployed on the compute node. Additionally, the compute node is configured to translate the network function profile usable to identify which of the plurality of network functions are to be managed by each of the plurality of interconnected hardware resources into a hardware profile for each of a plurality of interconnected hardware resources. The compute node is further configured to deploy each of the plurality of network functions to one or more of the plurality of interconnected hardware resources based on the hardware profile. Other embodiments are described herein.Type: ApplicationFiled: May 9, 2023Publication date: November 9, 2023Inventors: Andrey Chilikin, Sugesh Chandran
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Patent number: 11681565Abstract: Technologies for the hierarchical clustering of hardware resources in network function virtualization (NFV) deployments include a compute node that is configured to create a network function profile that includes a plurality of network functions to be deployed on the compute node. Additionally, the compute node is configured to translate the network function profile usable to identify which of the plurality of network functions are to be managed by each of the plurality of interconnected hardware resources into a hardware profile for each of a plurality of interconnected hardware resources. The compute node is further configured to deploy each of the plurality of network functions to one or more of the plurality of interconnected hardware resources based on the hardware profile. Other embodiments are described herein.Type: GrantFiled: September 13, 2018Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Andrey Chilikin, Sugesh Chandran
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Patent number: 11646980Abstract: Technologies for packet forwarding under ingress queue overflow conditions includes a computing device configured to receive a network packet from another computing device, determine whether a global packet buffer of the NIC is full, and determine, in response to a determination that the global packet buffer is full, whether to forward all the global packet buffer entries. The computing device is additionally configured to compare, in response to a determination not to forward all the global packet buffer entries, a selection filter to one or more characteristics of the received network packet and forward, in response to a determination that the selection filter matches the one or more characteristics of the received network packet, the received network packet to a predefined output. Other embodiments are described herein.Type: GrantFiled: March 30, 2018Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Andrey Chilikin, Vadim Sukhomlinov
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Patent number: 11641608Abstract: Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.Type: GrantFiled: February 25, 2021Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Jonas Svennebring, Niall D. McDonnell, Andrey Chilikin, Andrew Cunningham, Christopher MacNamara, Carl-Oscar Montelius, Eliezer Tamir, Bjorn Topel
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Publication number: 20230055703Abstract: An apparatus is described. The apparatus includes queue assignment circuitry. The queue assignment circuitry includes first circuitry to select amongst multiple hash keys and second circuitry to hash content of a packet's header with a selected one of the hash keys.Type: ApplicationFiled: November 8, 2022Publication date: February 23, 2023Inventors: Andrey CHILIKIN, Vladimir MEDVEDKIN, Elazar COHEN
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Patent number: 11539660Abstract: Examples include a computing system having a plurality of processing cores and a memory coupled to the plurality of processing cores. The memory has instructions stored thereon that, in response to execution by a selected one of the plurality of processing cores, cause the following actions. The selected processing core to receive a packet and get an original tuple from the packet. When no state information for a packet flow of the packet exists in a state table, select a new network address as a new source address for the packet, get a reverse tuple for a reverse direction, select a port for the packet from an entry in a mapping table based on a hash procedure using the reverse tuple, and save the new network address and selected port. Translate the packet's network address and port and transmit the packet.Type: GrantFiled: April 5, 2021Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: Vladimir Medvedkin, Andrey Chilikin
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Publication number: 20220385534Abstract: Examples described herein relate to a network interface device comprising circuitry and data plane circuitry. In some examples, the circuitry is to receive control configurations from multiple control planes and based on a management configuration, selectively deny a control configuration of the received control configurations to configure operations of the data plane circuitry.Type: ApplicationFiled: August 5, 2022Publication date: December 1, 2022Inventors: Elazar COHEN, Keren GUY, Marina POPILOV, Andrey CHILIKIN
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Publication number: 20220350676Abstract: Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Eliezer Tamir, Johannes Berg, Andrew Cunningham, Peter Waskiewicz, JR., Andrey Chilikin
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Patent number: 11483245Abstract: Technologies for filtering network traffic on ingress include a network interface controller (NIC) configured to parse a header of a network packet received by the NIC to extract data from a plurality of header fields of the header. The NIC is additionally configured to determine an input set based on the field vector, retrieve a matching list from a plurality of matching lists, and compare the input set to each of the plurality of rules to identify a matching rule of the plurality of rules that matches a corresponding portion of the input set. The NIC is further configured to perform an action on the network packet based on an actionable instruction associated with the one of the plurality of rules that matches the corresponding portion of the input set. Other embodiments are described herein.Type: GrantFiled: September 13, 2018Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Andrey Chilikin, Ronen Aharon Hyatt, Vadim Sukhomlinov
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Patent number: 11474879Abstract: Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.Type: GrantFiled: September 25, 2020Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Eliezer Tamir, Johannes Berg, Andrew Cunningham, Peter Waskiewicz, Jr., Andrey Chilikin
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Patent number: 11474878Abstract: Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.Type: GrantFiled: July 20, 2020Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Eliezer Tamir, Johannes Berg, Andrew Cunningham, Peter Waskiewicz, Jr., Andrey Chilikin
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Patent number: 11394666Abstract: Particular embodiments described herein provide for a system for enabling communication between a packet processing unit and a network interface controller (NIC) using an extension object, the system can include memory, one or more processors, and a processing unit extension object engine. The processing unit extension object engine can be configured to cause a packet to be received at the packet processing unit, where the packet processing unit is on a system on chip (SoC), add an extension object portion to the packet to create a modified packet, and cause the modified packet to be communicated to the NIC located on the same SoC. In an example, the extension object portion includes type data and partition data. The packet can be an Ethernet packet and the extension object portion can be added before a payload portion of the packet.Type: GrantFiled: December 18, 2017Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Anjali S. Jain, Donald Skidmore, Parthasarathy Sarangam, Joshua A. Hay, Ronen Chayat, Andrey Chilikin