Abstract: An approach is described for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools. According to some embodiments, the approach includes identification of a waiver of an error or warning, registration of one or more condition sets for waiver of an error or warning, waiver of multiple errors or warnings that match the registered one or more condition sets, and further comprise any or all of the following: receiving or retrieving a circuit design, analyzing the circuit design to identify errors and warnings, and displaying identified errors and warnings where errors and warnings matching a registered condition set are waived. This approach provides for a 1-to-many relationship between identification of a waiver and application of waivers.

Abstract: An approach is described for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools. According to some embodiments, the approach includes identification of a waiver of an error or warning, registration of one or more condition sets for waiver of an error or warning, waiver of multiple errors or warnings that match the registered one or more condition sets, and further comprise any or all of the following: receiving or retrieving a circuit design, analyzing the circuit design to identify errors and warnings, and displaying identified errors and warnings where errors and warnings matching a registered condition set are waived. This approach provides for a 1-to-many relationship between identification of a waiver and application of waivers.

Abstract: The present disclosure relates to a system and method for constraint validation in an electronic design. The method may include receiving an electronic design at an electronic design automation application and analyzing at least a portion of the electronic design at a constraint validation tool configured to analyze one or more physical constraints in a design layout associated with the electronic design. The method may further include applying one or more programmable electrical rule check (“PERC”) rules and one or more constraints to the electronic design, wherein the one or more PERC rules are configured to perform one or more electrical rule checks.

Abstract: A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-to's denoting start and end points for each route by invoking a star_route command in a router that implements interconnections as specified. Routing results are validated by checking for routing violations, including shared segments and width violations. Violations are marked for correction.

Abstract: The present disclosure relates to a system and method for constraint validation in an electronic design. The method may include receiving an electronic design at an electronic design automation application and analyzing at least a portion of the electronic design at a constraint validation tool configured to analyze one or more physical constraints in a design layout associated with the electronic design. The method may further include applying one or more programmable electrical rule check (“PERC”) rules and one or more constraints to the electronic design, wherein the one or more PERC rules are configured to perform one or more electrical rule checks.

Abstract: A system, method, and computer program product for automating the design and routing of non-shared one-to-many conductive pathways between a common pad and circuit blocks in an integrated circuit. Such pathways are routinely required for power and signal distribution purposes. Automated scripts perform a star routing methodology and validate the routing results. The methodology processes input width and layer constraints and from-to's denoting start and end points for each route by invoking a star_route command in a router that implements interconnections as specified. Routing results are validated by checking for routing violations, including shared segments and width violations. Violations are marked for correction.