Patents by Inventor Andrey Godkin

Andrey Godkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for threshold logic with electrostatically formed nanowire transistors
    Patent number: 10002964
    Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 19, 2018
    Assignee: Northwestern University
    Inventors: Joseph S. Friedman, Alan V. Sahakian, Andrey Godkin, Alex Henning, Yossi Rosenwaks
  • SYSTEM AND METHOD FOR THRESHOLD LOGIC WITH ELECTROSTATICALLY FORMED NANOWIRE TRANSISTORS
    Publication number: 20170309747
    Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.
    Type: Application
    Filed: July 7, 2017
    Publication date: October 26, 2017
    Inventors: Joseph S. Friedman, Alan V. Sahakian, Andrey Godkin, Alex Henning, Yossi Rosenwaks
  • System and method for threshold logic with electrostatically formed nanowire transistors
    Patent number: 9728636
    Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 8, 2017
    Assignees: NORTHWESTERN UNIVERSITY, RAMOT AT TEL AVIV UNIVERSITY LTD.
    Inventors: Joseph S. Friedman, Alan V. Sahakian, Andrey Godkin, Alex Henning, Yossi Rosenwaks
  • System and Method for Threshold Logic with Electrostatically Formed Nanowire Transistors
    Publication number: 20150279990
    Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 1, 2015
    Inventors: Joseph S. Friedman, Alan V. Sahakian, Andrey Godkin, Alex Henning, Yossi Rosenwaks