Patents by Inventor Andrey P. Plis

Andrey P. Plis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6564366
    Abstract: A channel routing method (200) comprises computing channel parameters (210), classifying a channel complexity and estimating a channel height (220), optionally, determining a trunk placement direction (225), assigning tracks and layers (230), determining a quality function QF (240), and optimizing (250). The channel complexity is classified using predetermined weighting parameters (a1 to a4). This classification selects a significance vector n. In the assigning step (230), the vector n is combined with the channel parameters to a criterion. The criterion is used the select the most suitable assignment. In repetitions of assigning, determining QF and optimizing steps, the significance vector n and, optionally, QF are modified. The repetition are stopped upon compliance of a breaking condition which can refer to QF.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: May 13, 2003
    Assignee: Motorola, Inc.
    Inventors: Alexander M. Marchenko, Andrey P. Plis, Mikhail A. Sotnikov, Patrick McGuinness
  • Patent number: 6477692
    Abstract: The invention concerns a method for manufacturing an electronic device having a channel. The channel has a number of rows and columns for wiring of nets. Usually each wiring layer is dedicated to either the rows or the columns. According to this method certain row segments can be shifted from one wiring layer to another, so that the channel area is used more effectively.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: November 5, 2002
    Assignee: Motorola, Inc.
    Inventors: Alexander Marchenko, Andrey P. Plis, Eugene G. Shiro, Mikhail A. Sotnikov, Igor Topouzov, Patrick McGuiness
  • Patent number: 6412103
    Abstract: In an improved routing method vertical constraint graph is generated in which a critical node is selected. The critical node is expanded to contain corresponding terminals. The resulting subnodes within the critical node are interconnected by edges that are representative of vertical constraints. A graph coloring method is employed to split the critical node into a number of new nodes. Thereby it is possible to route channels having multi-dimensional vertical constrains.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: June 25, 2002
    Assignee: Motorola Inc.
    Inventors: Alexander Marchenko, Andrey P. Plis, Vijayan Gopalakrishnan