Abstract: The present disclosure provides systems and methods for dynamically predicting and enhancing energy efficiency. Dynamically predicting and enhancing energy efficiency can include determining that the code path for the code executed at run time comprises a branch, selecting a path, corresponding to one of the plurality of versions of the code, from the branch based on the plurality of predictors, the plurality of metrics, and the plurality of versions of the code, and providing the code associated with the path to a processing unit for execution.

Abstract: An apparatus is described that includes a processor. The processor has a processing core to execute an instruction that specifies a performance state of an application thread. The instruction belongs to the application thread. The processor includes a register to store the performance state. The processor includes power management control logic coupled to the register to set a performance state of the processing core as a function of the performance state.

Abstract: In a data processing system that is executing a parent execution entity of an application, the parent execution entity has a first affinity setting. The data processing system enables the parent execution entity to create a worker execution entity that has a second affinity setting without changing the affinity setting of the parent execution entity. Workload for the application may then be performed in parallel by the parent execution entity and the worker execution entity. In one embodiment, to create the worker execution entity with the second affinity setting, the system first creates a delegate execution entity that has the first affinity setting. The system then changes the affinity setting of the delegate execution entity to the second affinity setting. The delegate execution entity then creates the worker execution entity with the second affinity setting. Another embodiment involves a super-delegate execution entity. Other embodiments are described and claimed.

Abstract: Methods, systems and apparatuses for processor selection in multi-processor systems are disclosed. An example method includes, for each of a plurality of processors, retrieving a list of interrupt instances for a plurality of interrupt types; calculating an interrupt instance count value for each of the plurality of interrupt types; multiplying a corresponding weighting factor by the interrupt instance count value for each one of the plurality of interrupt types to generate a plurality of weighted interrupt values; calculating an overall weighted vector value based on the sum of the plurality of weighted interrupt values; and designating one of the plurality of processors as a selected processor based on the lowest overall weighted vector value.

Abstract: In a data processing system that is executing a parent execution entity of an application, the parent execution entity has a first affinity setting. The data processing system enables the parent execution entity to create a worker execution entity that has a second affinity setting without changing the affinity setting of the parent execution entity. Workload for the application may then be performed in parallel by the parent execution entity and the worker execution entity. In one embodiment, to create the worker execution entity with the second affinity setting, the system first creates a delegate execution entity that has the first affinity setting. The system then changes the affinity setting of the delegate execution entity to the second affinity setting. The delegate execution entity then creates the worker execution entity with the second affinity setting. Another embodiment involves a super-delegate execution entity. Other embodiments are described and claimed.

Abstract: Methods, systems and apparatuses for processor selection in multi-processor systems are disclosed. An example method includes, for each of a plurality of processors, retrieving a list of interrupt instances for a plurality of interrupt types; calculating an interrupt instance count value for each of the plurality of interrupt types; multiplying a corresponding weighting factor by the interrupt instance count value for each one of the plurality of interrupt types to generate a plurality of weighted interrupt values; calculating an overall weighted vector value based on the sum of the plurality of weighted interrupt values; and designating one of the plurality of processors as a selected processor based on the lowest overall weighted vector value.

Abstract: An apparatus is described that includes a processor. The processor has a processing core to execute an instruction that specifies a performance state of an application thread. The instruction belongs to the application thread. The processor includes a register to store the performance state. The processor includes power management control logic coupled to the register to set a performance state of the processing core as a function of the performance state.