Patents by Inventor Andrey Vyatskikh

Andrey Vyatskikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113520
    Abstract: Techniques and mechanisms for a transition metal dichalcogenide (TMD) material to be grown on one structure, and then transferred to a different structure. In an embodiment, one or more monolayers of a TMD material are grown on a workpiece comprising a substrate, a growth layer, and a release layer. A material of the substrate is transparent to a wavelength of a laser light, wherein the release layer is opaque to said wavelength. The resulting material stack is then coupled to a target structure, after which a laser ablation is performed to remove some or all of the release layer from between the substrate and the growth layer. The ablation enables the substrate to be separated from the one or more monolayers. In an embodiment, a residue on a surface of the one or more TMD monolayers is an artefact of the layer transfer process.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Andrey Vyatskikh, Paul Fischer, Paul Nordeen, Kevin O'Brien, Chelsey Dorow, Carl H. Naylor, Uygar Avci
  • Publication number: 20250112077
    Abstract: An embodiment discloses an electronic device comprising an integrated circuit (IC) die, a stub extending from the IC die; and a mesa structure under the IC die, wherein the IC die and the stub are bonded to the mesa structure.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Andrey Vyatskikh, Adel Elsherbini, Brandon M. Rawlings, Tushar Kanti Talukdar, Thomas L. Sounart, Kimin Jun, Johanna Swan, Grant M. Kloster, Carlos Bedoya Arroyave
  • Publication number: 20250112122
    Abstract: Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: INTEL CORPORATION
    Inventors: Kevin P. O'Brien, Paul Gutwin, David L. Kencke, Mahmut Sami Kavrik, Daniel Chanemougame, Ashish Verma Penumatcha, Carl Hugo Naylor, Kirby Maxey, Uygar E. Avci, Tristan A. Tronic, Chelsey Dorow, Andrey Vyatskikh, Rachel A. Steinhardt, Chia-Ching Lin, Chi-Yin Cheng, Yu-Jin Chen, Tyrone Wilson
  • Publication number: 20250113547
    Abstract: Integrated circuit structures having internal spacers for 2D channel materials, and methods of fabricating integrated circuit structures having internal spacers for 2D channel materials, are described. For example, an integrated circuit structure includes a stack of two-dimensional (2D) material nanowires. A gate structure is vertically around the stack of 2D material nanowires. Internal gate spacers are between vertically adjacent ones of the stack of 2D material nanowires and laterally adjacent to the gate structure. The 2D material nanowires are recessed relative to the internal gate spacers. Conductive contact structures are at corresponding ends of the stack of 2D material nanowires, the conductive contact structures adjacent to the internal gate spacers and vertically overlapping with the internal gate spacers.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Chia-Ching LIN, Tao CHU, Chiao-Ti HUANG, Guowei XU, Robin CHAO, Feng ZHANG, Yue ZHONG, Yang ZHANG, Ting-Hsiang HUNG, Kevin P. O’BRIEN, Uygar E. AVCI, Carl H. NAYLOR, Mahmut Sami KAVRIK, Andrey VYATSKIKH, Rachel STEINHARDT, Chelsey DOROW, Kirby MAXEY
  • Publication number: 20250113573
    Abstract: A low strain transfer protective layer is formed on a transition metal dichalcogenide (TMD) monolayer to enable the transfer of the TMD monolayer from a growth substrate to a target substrate with little or no strain-induced damage to the TMD monolayer. Transfer of a TMD monolayer from a growth substrate to a target substrate comprises two transfers, a first transfer from the growth substrate to a carrier wafer and a second transfer from the carrier wafer to the target substrate. Transfer of the TMD monolayer from the growth substrate to the carrier wafer comprises mechanically lifting off the TMD monolayer from the growth substrate. The low strain transfer protective layer can limit the amount of strain transferred from the carrier wafer to the TMD monolayer during lift-off. The carrier wafer and protective layer are separated from the TMD monolayer after attachment of the TMD monolayer to the target substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Andrey Vyatskikh, Paul B. Fischer, Uygar E. Avci, Chelsey Dorow, Mahmut Sami Kavrik, Karthik Krishnaswamy, Chia-Ching Lin, Jennifer Lux, Kirby Maxey, Carl Hugo Naylor, Kevin P. O'Brien, Justin R. Weber
  • Publication number: 20250108459
    Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the third layer comprising a plurality of integrated circuit (IC) components, and applying a laser to ablate portions of the first layer, wherein the second layer protects the third layer from cracking during application of the laser.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: INTEL CORPORATION
    Inventors: Andrey Vyatskikh, Feras Eid, Tushar Kanti Talukdar, Kimin Jun, Thomas L. Sounart, Jeffery D. Bielefeld, Grant M. Kloster, Carlos Bedoya Arroyave, Golsa Naderi, Adel Elsherbini
  • Publication number: 20250113521
    Abstract: A transition metal dichalcogenide (TMD) monolayer grown on a growth substrate is directly transferred to a target substrate. Eliminating the use of a carrier wafer in the TMD monolayer transfer process reduces the number of transfers endured by the TMD monolayer from two to one, which can result in less damage to the TMD monolayer. After a TMD monolayer is grown on a growth layer, a protective layer is formed on the TMD monolayer. The protective layer is bonded to the target substrate by a diffusion bonding layer. The direct transfer of TMD monolayers can be repeated to create a stack of TMD monolayers. A stack of TMD monolayers can be used in a field effect transistor, such as a nanoribbon field effect transistor.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Andrey Vyatskikh, Paul B. Fischer, Paul Killian Nordeen, Uygar E. Avci, Mahmut Sami Kavrik, Ande Kitamura, Kirby Maxey, Carl Hugo Naylor, Kevin P. O'Brien
  • Publication number: 20250112196
    Abstract: An embodiment discloses an electronic device, comprising an integrated circuit (IC) die, a mesa structure formed on the IC die, and a die bonded to the IC die through the mesa structure.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Feras Eid, Johanna Swan, Adel Elsherbini, Thomas L. Sounart, Tushar Kanti Talukdar, Brandon M. Rawlings, Kimin Jun, Andrey Vyatskikh, Shawna M. Liff
  • Publication number: 20250113572
    Abstract: Techniques and mechanisms for forming a gate dielectric structure and source or drain (S/D) structures on a monolayer channel structure of a transistor. In an embodiment, the channel structure comprises a two-dimensional (2D) layer of a transition metal dichalcogenide (TMD) material. During fabrication of the transistor structure, a layer of a dielectric material is deposited on the channel structure, wherein the dielectric material is suitable to provide a reaction, with a plasma, to produce a conductive material. While a first portion of the dielectric material is covered by a patterned structure, a second portion of the dielectric material is exposed to a plasma treatment to form a source or dielectric (S/D) electrode structure that adjoins the first portion. In another embodiment, the dielectric material is an oxide of a Group V-VI transition metal.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Mahmut Sami Kavrik, Uygar E. Avci, Kevi P. Obrien, Chia-Ching Lin, Carl H. Naylor, Kirby Maxey, Andrey Vyatskikh, Scott B. Clendenning, Matthew Metz, Marko Radosavljevic
  • Publication number: 20250113540
    Abstract: Techniques and mechanisms for providing gate dielectric structures of a transistor. In an embodiment, the transistor comprises a thin channel structure which comprises one or more layers of a transition metal dichalcogenide (TMD) material. The channel structure forms two surfaces on opposite respective sides thereof, wherein the surfaces extend to each of two opposing edges of the channel structure. A composite gate dielectric structure comprises first bodies of a first dielectric material, wherein the first bodies each adjoin a different respective one of the two opposing edges, and variously extend to each of the surfaces two surfaces. The composite gate dielectric structure further comprises another body of a second dielectric material other than the first dielectric material. In another embodiment, the other body adjoins one or both of the two surfaces, and extends along one or both of the two surfaces to each of the first bodies.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Carl H. Naylor, Rachel Steinhardt, Mahmut Sami Kavrik, Chia-Ching Lin, Andrey Vyatskikh, Kevin O’Brien, Kirby Maxey, Ashish Verma Penumatcha, Uygar Avci, Matthew Metz, Chelsey Dorow
  • Publication number: 20250112092
    Abstract: An embodiment discloses a method comprising receiving a substrate comprising a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer comprising at least one integrated circuit (IC) component, the third layer comprising at least one dielectric material; and using a laser to weaken the first layer to facilitate separation of the second layer from the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corportation
    Inventors: Thomas L. Sounart, Adel Elsherbini, Feras Eid, Tushar Kanti Talukdar, Andrey Vyatskikh
  • Publication number: 20250112208
    Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a microelectronic assembly includes a solid glass layer, a plurality of mesa structures on a surface of the glass layer, and an integrated circuit (IC) component on each respective mesa structure. The mesa structures have similar footprints as the IC components, and may be formed on or integrated with the glass layer.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Thomas L. Sounart, Feras Eid, Kimin Jun, Tushar Kanti Talukdar, Andrey Vyatskikh, Johanna Swan, Shawna M. Liff
  • Publication number: 20250107147
    Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Mahmut Sami Kavrik, Uygar E. Avci, Pratyush P. Buragohain, Chelsey Dorow, Jack T. Kavalieros, Chia-Ching Lin, Matthew V. Metz, Wouter Mortelmans, Carl Hugo Naylor, Kevin P. O'Brien, Ashish Verma Penumatcha, Carly Rogan, Rachel A. Steinhardt, Tristan A. Tronic, Andrey Vyatskikh
  • Publication number: 20250105046
    Abstract: Methods of selectively transferring portions of layers between substrates, and devices and systems formed using the same, are disclosed herein. In one embodiment, a first substrate with a layer of integrated circuit (IC) components is received, and a second substrate with one or more adhesive areas is received. The first substrate is partially bonded to the second substrate, such that a subset of IC components on the first substrate are bonded to the adhesive areas on the second substrate. The first substrate is then separated from the second substrate, and the subset of IC components bonded to the second substrate are separated from the first substrate and remain on the second substrate.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Thomas L. Sounart, Feras Eid, Tushar Kanti Talukdar, Brandon M. Rawlings, Andrey Vyatskikh, Carlos Bedoya Arroyave, Kimin Jun, Shawna M. Liff, Grant M. Kloster, Richard F. Vreeland, William P. Brezinski, Johanna Swan
  • Patent number: 12226956
    Abstract: Methods and apparatuses for additive manufacturing are described. A method for additive manufacturing may include exposing a layer of material on a build surface to one or more projections of laser energy including at least one line laser having a substantially linear shape. The intensity of the line laser may be modulated so as to cause fusion of the layer of material according to a desired pattern as the one or more projections of laser energy are scanned across the build surface.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: February 18, 2025
    Assignee: VulcanForms Inc.
    Inventors: Martin C. Feldmann, Anastasios John Hart, Knute Svenson, Andrey Vyatskikh
  • Publication number: 20230219290
    Abstract: Methods and apparatuses for additive manufacturing are described. A method for additive manufacturing may include exposing a layer of material on a build surface to one or more projections of laser energy including at least one line laser having a substantially linear shape. The intensity of the line laser may be modulated so as to cause fusion of the layer of material according to a desired pattern as the one or more projections of laser energy are scanned across the build surface.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 13, 2023
    Applicant: VulcanForms Inc.
    Inventors: Martin C. Feldmann, Anastasios John Hart, Knute Svenson, Andrey Vyatskikh
  • Patent number: 11602792
    Abstract: Methods and apparatuses for additive manufacturing are described. A method for additive manufacturing may include exposing a layer of material on a build surface to one or more projections of laser energy including at least one line laser having a substantially linear shape. The intensity of the line laser may be modulated so as to cause fusion of the layer of material according to a desired pattern as the one or more projections of laser energy are scanned across the build surface.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: March 14, 2023
    Assignee: VulcanForms Inc.
    Inventors: Martin C. Feldmann, Anastasios John Hart, Knute Svenson, Andrey Vyatskikh
  • Patent number: 11442362
    Abstract: This disclosure provides a scalable and reproducible process to create complex 3D metal materials with sub-micron features by applying lithographic methods to transparent metal- or inorganic-rich polymer resins.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 13, 2022
    Assignee: California Institute of Technology
    Inventors: Andrey Vyatskikh, Stephane J. Delalande, Julia R. Greer
  • Publication number: 20210170490
    Abstract: Methods and apparatuses for additive manufacturing are described. A method for additive manufacturing may include exposing a layer of material on a build surface to one or more projections of laser energy including at least one line laser having a substantially linear shape. The intensity of the line laser may be modulated so as to cause fusion of the layer of material according to a desired pattern as the one or more projections of laser energy are scanned across the build surface.
    Type: Application
    Filed: January 25, 2021
    Publication date: June 10, 2021
    Applicant: VulcanForms Inc.
    Inventors: Martin C. Feldmann, Anastasios John Hart, Knute Svenson, Andrey Vyatskikh
  • Patent number: 10919090
    Abstract: Methods and apparatuses for additive manufacturing are described. A method for additive manufacturing may include exposing a layer of material on a build surface to one or more projections of laser energy including at least one line laser having a substantially linear shape. The intensity of the line laser may be modulated so as to cause fusion of the layer of material according to a desired pattern as the one or more projections of laser energy are scanned across the build surface.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: February 16, 2021
    Assignee: VulcanForms Inc.
    Inventors: Martin C. Feldmann, Anastasios John Hart, Knute Svenson, Andrey Vyatskikh