Abstract: In one embodiment, a method of fabricating one or more transistors in an integrated circuit includes an annealing step prior to a gate oxidation step. The annealing step may comprise a rapid thermal annealing (RTA) step performed prior to a gate oxidation pre-clean step. Among other advantages, the annealing step reduces a step height difference between P-doped and N-doped regions of a field oxide of a shallow trench isolation structure. The shallow trench isolation structure may be separating a PMOS transistor and an NMOS transistor in the integrated circuit.

Abstract: A method of forming a polished semiconductor structure comprises polishing a surface of a semiconductor structure by chemical mechanical polishing. Pressure applied to the surface is reduced during the polishing, or a rotation rate of a polishing surface relative to the surface is reduced during the polishing.

Abstract: A method and a system are provided for removing matter adhered to such a polishing pad. In particular, a polishing system is provided which is adapted to remove matter adhered to a polishing pad during a polishing process of a semiconductor topography. The polishing system may include a polishing pad and a spray element, which is preferably adapted to spray a pressurized fluid upon the polishing pad to remove matter adhered to the pad. In addition, a spray element is provided which may be adapted to be positioned within a polishing system. Such a spray element may be adapted to remove matter adhered to a polishing pad within the system by spraying a pressurized fluid upon the polishing pad. In addition, methods for cleaning a polishing pad during a polishing process and polishing multiple semiconductor topographies using the systems described herein are provided.

Abstract: A method is provided for processing a semiconductor topography. In an embodiment, the method includes polishing the topography on a primary polishing pad during a primary polishing step without depositing water on the primary polishing pad. The method may also include transferring the topography from the primary polishing pad to a final polishing pad. A substantial amount of residual slurry particles may be present on the topography while the topography is being transferred. In an embodiment, the method may also include polishing the topography on a final polishing pad during a final polishing step. The final polishing step may include depositing water on the final polishing pad in a plurality of dispense intervals to reduce a rate of change of a pH of a polishing solution on the topography.

Abstract: According to one embodiment, a shallow trench isolation (STI) method (500) may include forming an etch mask layer over both a first and second substrate side (504). An etch mask layer over a first substrate side (506) may be patterned to form a STI etch mask, and trenches may be etched into a substrate (508). A trench dielectric layer can be formed over a first substrate side (510). An etch mask layer formed over a second substrate side can be etched (512), reducing and/or eliminating stress that may deform a substrate or otherwise adversely affect STI features. A trench dielectric may then be chemically-mechanically polished (step 514).