Abstract: A radar receiver comprising: an ADC (510) that samples analogue intermediate frequency, IF, signalling in order to generate digital signalling, wherein the digital signalling comprises a plurality of digital-values; a digital processor that populates a 2-dimensional array of bin-values based on the digital-values, such that: a first axis of the 2-dimensional array is a fast time axis and a second axis of the 2-dimensional array is a slow time axis; and a sampling-rate-adjuster that is configured to set a sampling rate associated with the bin-values in the 2-dimensional array based on an index of the slow time axis. The digital processor also performs DFT calculations on the bin-values in the 2-dimensional array along the fast time axis and the slow time axis in order to determine the range and velocity of any detected objects.

Abstract: A receiver for receiving an input signal is disclosed. The receiver includes a processor, a memory, a plurality of sub-receivers configured to receive a plurality of versions of the input signal through a plurality of transmission channels, a sub-receiver selection module configured to select one more of the plurality of sub-receivers using expected contributions to signal-to-noise (SNR) of an output signal based on an uncertainty of the estimated contributions. The receiver also includes a combiner to combine outputs of the selected sub-receivers to produce the output signal.

Abstract: A receiver for receiving an input signal is disclosed. The receiver includes a processor, a memory, a plurality of sub-receivers configured to receive a plurality of versions of the input signal through a plurality of transmission channels, a sub-receiver selection module configured to select one more of the plurality of sub-receivers using expected contributions to signal-to-noise (SNR) of an output signal based on an uncertainty of the estimated contributions. The receiver also includes a combiner to combine outputs of the selected sub-receivers to produce the output signal.

Abstract: A processor (110) is disclosed for processing a plurality of Fourier-transformed instances of a symbol, each instance being comprised in one of a plurality of frequency-divided multiplexed subcarriers, said processor being arranged to estimate, for each instance, the channel gain and the inter-carrier interference contribution to said symbol from neighboring subcarriers due to a time-varying channel response of the received signal, and combine the instances into a single representation of said symbol based on the estimated channel gain and the inter-carrier interference contributions. A receiver comprising such a processor and a method for processing such signals are also disclosed.

Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Abstract: Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.

Abstract: Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

Abstract: A method is disclosed of compensating the output of an ADC for non-linearity in the response of the ADC. The method comprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables.

Abstract: A method for driving a light source (11, 12, 13) is described, wherein the light source is alternately switched ON and OFF in an ON/OFF pattern, wherein the duty cycle of the ON/OFF pattern is varied to vary the average light intensity of the light source, and wherein the shape of the ON/OFF pattern is varied to transmit data. Thus, a control signal for the light source comprises data information as well as duty cycle information. The duty cycle is varied within a range from almost zero to almost 100%, and data is varied and transmitted without affecting the duty cycle.

Abstract: Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Abstract: A processor (110) is disclosed for processing a plurality of Fourier-transformed instances of a symbol, each instance being comprised in one of a plurality of frequency-divided multiplexed subcarriers, said processor being arranged to estimate, for each instance, the channel gain and the inter-carrier interference contribution to said symbol from neighboring subcarriers due to a time-varying channel response of the received signal, and combine the instances into a single representation of said symbol based on the estimated channel gain and the inter-carrier interference contributions. A receiver comprising such a processor and a method for processing such signals are also disclosed.

Abstract: Various embodiments relate to a storage unit and a related method in a Viterbi decoder for decoding a binary convolutional code with power efficiency. A storage unit for storing survivor paths may use a register exchange method to append additional information received from an add-compare-select unit onto the end of the survivor path. An exemplary method produces a prediction path after a specified depth in the survivor path processing history and subtracts the prediction path from the survivor path. This may cause a majority of bits that comprise the survivor path to be converted to a low-energy bit, such as a logical “0”. During subsequent copies of a differential survivor path using the register exchange method, less energy is consumed when copying the entire survivor path, as a majority of the bits in the survivor paths are a logical “0”.

Abstract: A method is disclosed of compensating the output of an ADC for non-linearity in the response of the ADC. The method comprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables.

Abstract: The present invention relates to SISO decoder for iteratively decoding a block of received information symbols (r), in particular for use in a turbo decoder, said block being divided into a number of windows of information symbols. In order to achieve a significant reduction of power consumption a SISO decoder is proposed comprising at least one SISO decoding unit (17, 21) for SISO decoding of the received information symbols (r) of a window, wherein a stopping criterion is applied to each window. This allows to abort iterative decoding for each window individually once convergence of decoding is determined by marking a window or sub-block inactive (17,23). An inactive window is no longer SISO decoded in subsequent iterations.

Abstract: A coder converts M-bit information words into N-bit code words by generating a first and a second provisional code sequence using a coding rule by which, code words are logically assigned to information words so that a two's complement of a sum of coding bits included in the first provisional code sequence, is always different from a two's complement of a sum of coding bib included in the second provisional code sequence, when a first code state of the first sequence encoded starting from a predetermined original state is identical to a second code state of the second sequence encoded starting from said predetermined original state. Then, selecting either the first sequence or the second sequence depending on a value of at least one parameter that correlates with a DC content of the coded bit stream.

Abstract: A method for driving a light source (11, 12, 13) is described, wherein the light source is alternately switched ON and OFF in an ON/OFF pattern, wherein the duty cycle of the ON/OFF pattern is varied to vary the average light intensity of the light source, and wherein the shape of the ON/OFF pattern is varied to transmit data. Thus, a control signal for the light source comprises data information as well as duty cycle information. The duty cycle is varied within a range from almost zero to almost 100%, and data is varied and transmitted without affecting the duty cycle.

Abstract: The invention provides an efficient reading device in which, even if one radiation beam should fail, no information is lost and the information can still be read out without time-consuming recurring operations. The present invention solves this problem by providing a reading device (FIG. 5A) and a means (FIG. 4) for forming read-out spots (A, B, C, D, E) that are built up by multiple radiation beams from the radiation source (4). This has the advantage that each read-out spot will have energy contributions from different radiation beams and, should one radiation beam break down, the intensity of some of the read-out spots may indeed diminish, but the information can still be read out thanks to the contributions from other radiation beams.

Abstract: Methods and devices for objectively predicting perceptual quality of speech signals degraded in a speech processing/transporting system which may have poor prediction results for degraded signals including extremely weak or silent portions. Improvement is achieved by applying a first scaling step in a pre-processing stage with a first scaling factor which is a function of a reciprocal value of power of the output signal increased by an adjustment value, and by a second scaling step with a second scaling factor which is substantially equal to the first scaling factor raised to an exponential value and with an adjustment value between zero and one. The second scaling step may be performed at various locations in the device. The adjustment values are adjusted using test signals with well-defined subjective quality scores.

Abstract: Presently known d=1 codes have long trains consisting of consecutive 2T runs and an overall high frequency of occurrence of the shortest 2T runs that reduce the performance of the bit detector By using a code with an MTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an MTR constraint of 2 is presented. A variation of such a code is disclosed where one sub-code is used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index Tmax+1 t.