Patents by Inventor Androula G. Nassiopoulou

Androula G. Nassiopoulou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7233000
    Abstract: This invention provides a miniaturized silicon thermal flow sensor with improved characteristics, based on the use of two series of integrated thermocouples (6, 7) on each side of a heater (4), all integrated on a porous silicon membrane (2) on top of a cavity (3). Porous silicon (2) with the cavity (3) underneath provides very good thermal isolation for the sensor elements, so as the power needed to maintain the heater (4) at a given temperature is very low. The formation process of the porous silicon membrane (2) with the cavity (3) underneath is a two-step single electrochemical process. It is based on the fact that when the anodic current is relatively low, we are in a regime of porous silicon formation, while if this current exceeds a certain value we turn into a regime of electropolishing. The process starts at low current to form porous silicon (2) and it is then turned into electropolishing conditions to form the cavity (3) underneath.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: June 19, 2007
    Inventors: Androula G. Nassiopoulou, Grigoris Kaltsas, Dimitrios N. Pagonis
  • Publication number: 20040195096
    Abstract: This invention provides a front side silicon micromachining process for the fabrication of suspended Porous Silicon membranes in the form of bridges or cantilevers and of thermal sensor devices employing these membranes. The fabrication of the suspended Porous Silicon membranes comprises the following steps: (a) formation of a Porous Silicon layer (2) in, at least one, predefined area of a Silicon substrate (1), (b) definition of etch windows (5) around or inside said Porous Silicon layer (2) using standard photolithography and (c) selective etching of the silicon substrate (1), underneath the Porous Silicon layer (2), by using dry etching techniques to provide release of the Porous Silicon membrane and to form a cavity (6) under the said Porous Silicon layer.
    Type: Application
    Filed: January 30, 2004
    Publication date: October 7, 2004
    Inventors: Christos Tsamis, Angeliki Tserepi, Androula G Nassiopoulou