Abstract: A Low Voltage Differential Signaling Driver with Pre-emphasis and including a primary stage having a first switching circuit providing an output representing a sequence of pulses at a predetermined current level, a secondary stage having a second switching circuit arranged to provide an additional current level for the pulses, and a control circuit arranged to provide control signals for controlling the first and second switching circuits. The control circuit detects a difference in level between two consecutive pulses of the sequence and provides accordingly control signals to the first and second switching circuits. The control signals are such that when two consecutive pulses of the sequence are different, the additional current level is added to the predetermined current level, whilst when two consecutive pulses of the sequence are identical, the additional current level is subtracted from the predetermined current level.

Abstract: The present invention is related to a device comprising, between a differential pair of inputs, a differential pre-amplifier (HPA1, HPA2), an offset-reducing block (ORB) cascaded with said differential pre-amplifier (HPA1, HPA2) and arranged for reducing the offset generated by said differential pre-amplifier, and a buffering block (BB) in series with said offset-reducing block (ORB) and arranged for amplifying and buffering the output voltage of said offset-reducing block.

Abstract: The present invention is related to a device comprising, between a differential pair of inputs, a differential pre-amplifier (HPA1, HPA2), an offset-reducing block (ORB) cascaded with said differential pre-amplifier (HPA1, HPA2) and arranged for reducing the offset generated by said differential pre-amplifier, and a buffering block (BB) in series with said offset-reducing block (ORB) and arranged for amplifying and buffering the output voltage of said offset-reducing block.

Abstract: A Low Voltage Differential Signaling [LVDS] Driver with Pre-emphasis and comprising a primary stage (MP3-MP6, MN3-MN6) having a first switching circuit (MP5, MP6, MN5, MN6) arranged to provide a sequence of pulses (OUT1; OUT2) at a predetermined current level (I1), a secondary stage (MP7-MP9, MN7-MN9) having a second switching circuit (MP8, MP9, MN8, MN9) arranged to provide an additional current level (I2) for the pulses, and a control circuit arranged to provide control signals (A,{overscore (A)},B,{overscore (B)}) for controlling the first and second switching circuits. The control circuit is adapted to detect a difference in level between two consecutive pulses of the sequence and to provide accordingly control signals (A,{overscore (A)},B,{overscore (B)}) to the first (MP5, MP6, MN5, MN6) and second (MP8, MP9, MN8, MN9) switching circuits.

Abstract: A wideband common-mode regulation circuit for coupling a differential amplifier, or more particularly a Low Voltage Differential Signaling driver LVDS, to a load generally constituted by a telecommunication transmission line. The regulation circuit only comprises a first resistive pair (R1, R2) to sense the common-mode voltage at the differential input terminals (INP, INN), a second resistive pair (R3, R4) to force the voltage across the load to a predetermined value, and an active device (OTA, INV) coupled between the junction points of the first and the second resistive pairs. The active device is an Operational Transconductance Amplifier (OTA) or, preferably, an inverter (INV). Owing to reduced number of non-dominant poles in the common-mode open-loop transfer characteristic, this regulation circuit provides common-mode loop stability for wide common-mode loop bandwidth.