Patents by Inventor Andrzej Jakowski
Andrzej Jakowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210117123Abstract: An embodiment of an electronic apparatus may include a substrate, a local memory coupled to the substrate, and logic coupled to the substrate and the local memory, the logic to locally manage a rebuild of data on a persistent storage media in response to a rebuild initiation command, and utilize peer-to-peer communication to transfer data from a member drive to the local memory. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 24, 2020Publication date: April 22, 2021Applicant: Intel CorporationInventors: Andrzej Jakowski, Revanth Rajashekar
-
Patent number: 10877691Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a stream classification for an access request to a persistent storage media, and assign the access request to a stream based on the stream classification. Other embodiments are disclosed and claimed.Type: GrantFiled: December 29, 2017Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Mariusz Barczak, Dhruvil Shah, Kapil Karkra, Andrzej Jakowski, Piotr Wysocki
-
Patent number: 10635318Abstract: A technology is described for a logical storage driver. An example method can include using the logical storage driver to: forward requests to a first storage stack for processing of an I/O workload associated with the I/O requests. Initiate generation of trace data for the I/O workload for collection and analysis to determine a second storage stack for improving performance of the I/O workload. Receive the storage processing logic for processing the I/O workloads using the storage configuration for the I/O workload, where the storage processing logic interfaces with the storage configuration. Intercept the I/O requests that correspond to the I/O workload. And, process the I/O workloads using the storage processing logic that interfaces with the storage configuration.Type: GrantFiled: December 27, 2017Date of Patent: April 28, 2020Assignee: Intel CorporationInventors: Mariusz Barczak, Michal Wysoczanski, Andrzej Jakowski
-
Patent number: 10402338Abstract: In one embodiment, a processor comprises a processing core; and a cache controller to send a plurality of write requests to a cache storage device to store cache lines of a stream block, the plurality of write requests each including a stream identifier of the stream block, wherein a capacity of the stream block is equal to a capacity of an erase block of the cache storage device and wherein the erase block is dedicated to storing cache lines of the stream block; determine to evict the stream block from the cache storage device based upon a determination that space is not available in the cache storage device to cache data received from a first storage device; and send a deallocation request to the cache storage device to deallocate all cache lines of the stream block to enable the cache storage device to erase the erase block.Type: GrantFiled: April 1, 2017Date of Patent: September 3, 2019Assignee: Intel CorporationInventors: Andrzej Jakowski, Kapil Kumar Karkra
-
Patent number: 10331385Abstract: In one embodiment, a request to access a first storage location of a storage device may be received, wherein the storage device comprises a data storage and a cache. The cache may be accessed to obtain data for one or more second storage locations of the storage device, wherein the data for the one or more second storage locations has not been written to the data storage, and wherein the first storage location and the one or more second storage locations are located near each other on the data storage. The data storage may then be accessed in response to the request to access the first storage location of the storage device. The data storage may also be accessed to write the data for the one or more second storage locations obtained from the cache.Type: GrantFiled: September 29, 2016Date of Patent: June 25, 2019Assignee: Intel CorporationInventors: Andrzej Jakowski, Maciej Kaminski
-
Publication number: 20190095107Abstract: Systems and methods for issuing one or more write requests to a storage device, the system comprising one or more processors configured to generate one or more write requests, each write request comprising a respective data; tag each of the one or more write requests as a respective class from a plurality of classes, wherein the plurality of classes categorize data based on a rate at which it is written to the storage device; and issue the one or more write requests with their respective tags to the storage device, wherein the tag indicates to the storage device to write the first data proximate to data of the respective class within the storage device.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Michal WYSOCZANSKI, Andrzej JAKOWSKI, Kapil KARKRA
-
Publication number: 20190042451Abstract: A memory storage control apparatus, system, and method are described. An apparatus can include a memory controller configured to couple to a primary memory resource (PMR) and to a cache memory resource (CMR) and is configured to receive a read or write data request associated with particular data. For a read data request, the memory controller is configured to perform a lookup of a cache table mapped to the CMR for a copy of the particular data, and determine, if the lookup returns a hit and the particular data is not altered compared to the copy of the particular data, whether the CMR is saturated. For a write data request, the memory controller is configured to determine whether the CMR is saturated with data requests. In accordance with a determination that the CMR is saturated with data requests, the bypass the CMR, and send the data request to the PMR.Type: ApplicationFiled: February 20, 2018Publication date: February 7, 2019Inventors: DAVID J. LEONE, ANDRZEJ JAKOWSKI
-
Publication number: 20190042386Abstract: A technology is described for a logical storage driver. An example method can include using the logical storage driver to: forward requests to a first storage stack for processing of an I/O workload associated with the I/O requests. Initiate generation of trace data for the I/O workload for collection and analysis to determine a second storage stack for improving performance of the I/O workload. Receive the storage processing logic for processing the I/O workloads using the storage configuration for the I/O workload, where the storage processing logic interfaces with the storage configuration. Intercept the I/O requests that correspond to the I/O workload. And, process the I/O workloads using the storage processing logic that interfaces with the storage configuration.Type: ApplicationFiled: December 27, 2017Publication date: February 7, 2019Applicant: Intel CorporationInventors: MARIUSZ BARCZAK, MICHAL WYSOCZANSKI, ANDRZEJ JAKOWSKI
-
Publication number: 20190034120Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a stream classification for an access request to a persistent storage media, and assign the access request to a stream based on the stream classification. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 29, 2017Publication date: January 31, 2019Inventors: Mariusz Barczak, Dhruvil Shah, Kapil Karkra, Andrzej Jakowski, Piotr Wysocki
-
Patent number: 10146688Abstract: An embodiment of a cache apparatus may include a first cache memory, a second cache memory, and a cache controller communicatively coupled to the first cache memory and the second cache memory to allocate cache storage for clean data from one of either the first cache memory or the second cache memory, and allocate cache storage for dirty data from both the first cache memory and the second cache memory. Other embodiments are disclosed and claimed.Type: GrantFiled: December 29, 2016Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Maciej Kaminski, Andrzej Jakowski, Piotr Wysocki
-
Publication number: 20180285282Abstract: In one embodiment, a processor comprises a processing core; and a cache controller to send a plurality of write requests to a cache storage device to store cache lines of a stream block, the plurality of write requests each including a stream identifier of the stream block, wherein a capacity of the stream block is equal to a capacity of an erase block of the cache storage device and wherein the erase block is dedicated to storing cache lines of the stream block; determine to evict the stream block from the cache storage device based upon a determination that space is not available in the cache storage device to cache data received from a first storage device; and send a deallocation request to the cache storage device to deallocate all cache lines of the stream block to enable the cache storage device to erase the erase block.Type: ApplicationFiled: April 1, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Andrzej Jakowski, Kapil Kumar Karkra
-
Publication number: 20180189178Abstract: An embodiment of a cache apparatus may include a first cache memory, a second cache memory, and a cache controller communicatively coupled to the first cache memory and the second cache memory to allocate cache storage for clean data from one of either the first cache memory or the second cache memory, and allocate cache storage for dirty data from both the first cache memory and the second cache memory. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Maciej Kaminski, Andrzej Jakowski, Piotr Wysocki
-
Publication number: 20180089082Abstract: In one embodiment, a request to access a first storage location of a storage device may be received, wherein the storage device comprises a data storage and a cache. The cache may be accessed to obtain data for one or more second storage locations of the storage device, wherein the data for the one or more second storage locations has not been written to the data storage, and wherein the first storage location and the one or more second storage locations are located near each other on the data storage. The data storage may then be accessed in response to the request to access the first storage location of the storage device. The data storage may also be accessed to write the data for the one or more second storage locations obtained from the cache.Type: ApplicationFiled: September 29, 2016Publication date: March 29, 2018Applicant: Intel CorporationInventors: Andrzej Jakowski, Maciej Kaminski
-
APPARATUS AND METHOD FOR PERSISTING BLOCKS OF DATA AND METADATA IN A NON-VOLATILE MEMORY (NVM) CACHE
Publication number: 20180089088Abstract: Provided are an apparatus and method for persisting blocks of data and metadata in a non-volatile memory (NVM) cache. A non-volatile memory (NVM) cache caches blocks of data from the storage of the first block size and metadata for each of the cached blocks of data indicating a status of the cached block of data, including whether the block of data is modified or unmodified, and a location in the storage where the block of data is stored. The non-volatile memory has blocks of a second block size greater than the first block size, wherein one of the blocks in the non-volatile memory stores the block of data from the storage and the metadata for the block of data. A cache manager writes the block of data and the metadata for the block of data to one of the blocks in the non-volatile memory cache and writes the block of data in one of the blocks in the non-volatile memory cache to the storage.Type: ApplicationFiled: September 27, 2016Publication date: March 29, 2018Inventors: Andrzej JAKOWSKI, Kapil KARKRA, Igor KONOPKO, Sanjeev N. TRIKA, Knut S. GRIMSRUD