Abstract: A sealing frame arrangement is disclosed for creating a hermetic seal between two components or bodies such as a connector and heat sink module of an integrated circuit package. The frame members are configured to fit together along facing surfaces and to be joined to the two bodies along the inner edge of their outside (non-facing) surfaces. The sealing arrangement is completed by a third seal formed along the outer facing edge of the frames. The frames extend a sufficient distance beyond the two components to permit severing the frames inside the third seal and resealing. Preferably, the frames are of sufficient width to provide a multiplicity of sealing regions so that the third seal can be broken and resealed a number of times. The seal frames may be of stepped or corrugated configuration in which the individual seals are formed along the mating steps.

Abstract: A package for mounting and cooling a high density array of integrated circuit chips includes an interconnection assembly for the IC chips which (1) provides base connections to a printed circuit board (PCB), which is adapted to connect to external signal circuits, and (2) separate peripheral power supply connections. The package also includes a cooling module containing fluid-cooled heat sinks that (a) collectively conform to the array of integrated circuit chips and (b) individually conform to the configuration and orientation of the individual chips. The heat sinks are conformed to the chip orientation independently of the coolant flow, which is established through the heat sinks immediately adjacent the interface. Among other aspects of the package, the interconnection assembly incorporates resilient connectors that provide essentially stress-impervious connections to the integrated circuit chips and to the signal PCB.

Abstract: A module for a semiconductor chip is disclosed. The module includes a heat sink with a flat surface to which the back face of the semiconductor chip is directly bonded. The exposed face of the chip has an array of power, ground and signal contacts. A plurality of alternating power and ground bus bars span the exposed face of the chip. A multilayer ceramic is located on the other side of the bus bar array and has a surface proximate the power and ground bus bars with an array of contacts which correspond to at least the signal contacts on the chip. Power leads connect the power bus bars to adjacent power contacts on the chip; ground leads connect the ground bus bars to adjacent ground contacts on the chip; and signal leads pass between adjacent power and ground bus bars and interconnect the signal contacts on the chip with the corresponding signal contacts on the ceramic.

Abstract: A semiconductor chip having a two-dimensional array of contacts on an exposed face thereof is mounted in a semiconductor chip module. A mechanism for delivering electricity spans the exposed face of the chip to which it is connected and includes interstitial gaps. A conductor board has a surface proximate the electricity delivering mechanism opposite from the chip. The surface of the board has a two-dimensional array of contacts which correspond to at least some of the contacts on the chip. A biasing mechanism extends from the electricity delivering mechanism toward the exposed face of the semiconductor chip and toward the conductor board, and corresponds to the array of contacts on the chip and board. Signal leads pass through the interstitial gaps and have end portions which extend transversely over the biasing means. The end portions of the signal leads are biased against the contacts of the chips and board by the biasing mechanism.