Patents by Inventor Andrzej Rozbicki
Andrzej Rozbicki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220165645Abstract: Semiconductor devices are described. In one example, the semiconductor device includes a substrate, a layer of first semiconductor material over the substrate, a layer of second semiconductor material over the layer of first semiconductor material, a first metal contact formed on the layer of first semiconductor material, a second metal contact formed on the layer of second semiconductor material, and a metal via that extends from a backside of the substrate, through the substrate, through the layer of first semiconductor material, and contacts a bottom surface of the first metal contact. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact.Type: ApplicationFiled: February 8, 2022Publication date: May 26, 2022Inventors: Andrzej Rozbicki, Belinda Simone Edmee Piernas, David Russell Hoag, James Joseph Brogle, Timothy Edward Boles
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Publication number: 20220158320Abstract: Aspects of coaxial to microstrip transitional housings are described. In one example, a transitional housing includes a channel comprising sidewalls formed into the housing, and an opening formed at an end of the channel. The transitional housing also includes a plug that is fitted into the opening at an end of the channel. The plug has a flat surface positioned at the end of the channel, extending between the sidewalls of the channel, and an undercut below the flat surface. The transitional housing also includes a coaxial conductor aperture that extends from outside the housing, into the housing, into the plug, through the flat surface and undercut of the plug, and into the channel. Use of the plug offers a manufacturing solution for the mechanical and electrical transition between a coaxial feedthrough to a PCB microstrip secured within the housing. The solution helps to eliminate unwanted mismatches of the transition.Type: ApplicationFiled: November 18, 2020Publication date: May 19, 2022Inventors: Andrzej Rozbicki, Paul Hogan, Gary Pepelis, Scott Donahue
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Patent number: 11270928Abstract: A diode semiconductor structure is described. In one example, a diode device includes a substrate, a layer of first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact.Type: GrantFiled: April 2, 2020Date of Patent: March 8, 2022Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.Inventors: Andrzej Rozbicki, Belinda Simone Edmee Piernas, David Russell Hoag, James Joseph Brogle, Timothy Edward Boles
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Publication number: 20210367084Abstract: A diode structure and a method of fabrication of the diode structure is described. In one example, the diode structure is a PIN diode structure and includes an N-type layer formed on a substrate, an intrinsic layer formed on the N-type layer, and a P-type layer formed on the intrinsic layer. The P-type layer forms an anode of the diode structure, and the anode is formed as a quadrilateral-shaped anode. According to the embodiments, a top surface of the anode can be formed with one or more straight segments, such as a quadrilateral-shaped anode, to reduce at least one of a thermal resistance or an electrical on-resistance. These changes, among others, can improve the overall power handling capability of the PIN diode structure.Type: ApplicationFiled: August 6, 2021Publication date: November 25, 2021Inventors: Timothy Edward Boles, James Joseph Brogle, Andrzej Rozbicki, Belinda Simone Edmee Piernas, Daniel Gustavo Curcio, David Russell Hoag
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Publication number: 20210313250Abstract: A diode semiconductor structure is described. In one example, a diode device includes a substrate, a layer of first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact.Type: ApplicationFiled: April 2, 2020Publication date: October 7, 2021Inventors: Andrzej Rozbicki, Belinda Simone Edmee Piernas, David Russell Hoag, James Joseph Brogle, Timothy Edward Boles
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Publication number: 20190214335Abstract: In one example, a device having integrated package interference isolation includes a ground pad, an integrated circuit device die secured to the ground pad, a substrate secured to the ground pad, at least one a high-frequency, high-power semiconductor device secured to a top mounting surface of the substrate. For electromagnetic isolation, the integrated circuit device die includes a top metal, and the substrate includes a metal via electrically coupled to a metal trace that extends on the top mounting surface of the substrate. The device package also includes a number of ground pad bonding wires that electrically couple the redistribution layer of the integrated circuit device die and the metal trace to the ground pad. The redistribution layer of the integrated circuit device die and the metal trace and via of the substrate help to shield electromagnetic radiation between components in the device package.Type: ApplicationFiled: January 9, 2018Publication date: July 11, 2019Inventors: Andrzej Rozbicki, Chi Mo, Cristiano Bazzani
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Patent number: 10347571Abstract: In one example, a device having integrated package interference isolation includes a ground pad, an integrated circuit device die secured to the ground pad, a substrate secured to the ground pad, at least one a high-frequency, high-power semiconductor device secured to a top mounting surface of the substrate. For electromagnetic isolation, the integrated circuit device die includes a top metal, and the substrate includes a metal via electrically coupled to a metal trace that extends on the top mounting surface of the substrate. The device package also includes a number of ground pad bonding wires that electrically couple the redistribution layer of the integrated circuit device die and the metal trace to the ground pad. The redistribution layer of the integrated circuit device die and the metal trace and via of the substrate help to shield electromagnetic radiation between components in the device package.Type: GrantFiled: January 9, 2018Date of Patent: July 9, 2019Assignee: MACOM Technology Solutions Holdings, Inc.Inventors: Andrzej Rozbicki, Chi Mo, Cristiano Bazzani
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Patent number: 9538636Abstract: An apparatus having a plurality of insulating layers, a plurality of conductive layers and a plating is disclosed. The conductive layers may be separated by the insulating layers. A first pattern in a first of the conductive layers generally extends to an edge castellation. A second pattern in a second of the conductive layers may also extends to the edge castellation. The plating may be disposed in the edge castellation and connect the first pattern to the second pattern. The plating in the castellation may extend at most between a subset of the conductive layers.Type: GrantFiled: March 14, 2013Date of Patent: January 3, 2017Assignee: MACOM Technology Solutions Holdings, Inc.Inventors: Christopher D. Weigand, Andrzej Rozbicki