Abstract: The present disclosure relates to a neural network system comprising: a controller including a processing unit configured to execute a spiking neural network, and an interface connecting the controller to an external memory. The controller is configured for executing the spiking neural network, the executing comprising generating read instructions and/or write instructions. The interface is configured for: generating read weighting vectors according to the read instructions, coupling read signals, representing the read weighting vectors, into input lines of the memory, thereby retrieving data from the memory, generating write weighting vectors according to the write instructions, coupling write signals, representing the write weighting vectors, into output lines of the memory, thereby writing data into the memory.

Abstract: The present disclosure relates to a neuromorphic neuron apparatus comprising an output generation block and at least one adaptation block. The apparatus has a current adaptation state variable corresponding to previously generated one or more signals. The output generation block is configured to use an activation function for generating a current output value based on the current adaptation state variable. The adaptation block is configured to repeatedly: compute an adaptation value of its current adaptation state variable using the current output value and a correction function; use the adaption value to update the current adaptation state variable to obtain an updated adaptation state variable, the updated adaptation state variable becoming the current adaptation state variable; receive a current signal; and cause the output generation block to generate a current output value based on the current adaptation state variable and input value that obtained from the received signal.

Abstract: In a hardware-implemented approach for operating a neural network system, a neural network system is provided comprising a controller, a memory, and an interface connecting the controller to the memory, where the controller comprises a processing unit configured to execute a neural network and the memory comprises a neuromorphic memory device with a crossbar array structure that includes input lines and output lines interconnected at junctions via electronic devices. The electronic devices of the neuromorphic memory device are programmed to incrementally change states by coupling write signals into the input lines based on: write instructions received from the controller and write vectors generated by the interface. Data is retrieved from the neuromorphic memory device, according to a multiply-accumulate operation, by coupling read signals into one or more of the input lines of the neuromorphic memory device based on: read instructions from the controller and read vectors generated by the interface.

Abstract: The present disclosure relates to a storage device comprising a memory element. The memory element may comprise a changeable physical quantity for storing information. The physical quantity may be in a drifted state. The memory element may be configured for setting the physical quantity to an initial state. Furthermore, the memory element may comprise a drift of the physical quantity from the initial state to the drifted state. The initial state of the physical quantity may be computable by means of an initialization function. The initialization function may be dependent on a target state of the physical quantity and the target state of the physical quantity may be approximately equal to the drifted state of the physical quantity.

Abstract: Training a neural network that comprises nodes and weighted connections between selected ones of the nodes is described herein. A function of a desired activity and a current activity during training results in a feedback signal used for adjusting weight values of the connections. For a weight value update cycle the process determines an importance value for various nodes based on current weight values of the connections and determines an adjustment of the feedback signal specific for each weight value of the connections by a combination of a gradient value derived from the feedback signal for a connection and the determined corresponding element of the adjustment matrix. The updates are applied to the connections during update cycles.

Abstract: The present disclosure relates to an integrated circuit comprising a first neuromorphic neuron apparatus. The first neuromorphic neuron apparatus comprises an input and an accumulation block having a state variable for performing an inference task on the basis of input data comprising a temporal sequence. The first neuromorphic neuron apparatus may be switchable in a first mode and in a second mode. The accumulation block may be configured to perform an adjustment of the state variable using a current input signal of the first neuromorphic neuron apparatus and a decay function indicative of a decay behavior of the apparatus. The state variable may be dependent on previously received one or more input signals of the first neuromorphic neuron apparatus.

Abstract: The present disclosure relates to a storage device comprising a memory element. The memory element may comprise a changeable physical quantity for storing information. The physical quantity may be in a drifted state. The memory element may be configured for setting the physical quantity to an initial state. Furthermore, the memory element may comprise a drift of the physical quantity from the initial state to the drifted state. The initial state of the physical quantity may be computable by means of an initialization function. The initialization function may be dependent on a target state of the physical quantity and the target state of the physical quantity may be approximately equal to the drifted state of the physical quantity.

Abstract: A neural apparatus for a neural network system may be configured to receive one or more input signals during a decode time period, decode the one or more input signals during the decode time period, resulting in a decoded signal, and upon termination of the decode time period, process the decoded signal using internal neuron dynamics. The processed signal may be used to encode and emit one or more output signals in a subsequent decode time period to another neural apparatus of the neural network system.

Abstract: The invention is notably directed to a computer-implemented method for training parameters of a recurrent neural network. The network comprises one or more layers of neuronal units. Each neuronal unit has an internal state, which may also be denoted as unit state. The method comprises providing training data comprising an input signal and an expected output signal to the recurrent neural network. The method further comprises computing, for each neuronal unit, a spatial gradient component and computing, for each neuronal unit, a temporal gradient component. The method further comprises updating the temporal and the spatial gradient component for each neuronal unit at each time instance of the input signal. The computing of the spatial and the gradient component may be performed independently from each other. The invention further concerns a neural network and a related computer program product.

Abstract: The present disclosure relates to a neural network system comprising: a controller including a processing unit configured to execute a spiking neural network, and an interface connecting the controller to an external memory. The controller is configured for executing the spiking neural network, the executing comprising generating read instructions and/or write instructions. The interface is configured for: generating read weighting vectors according to the read instructions, coupling read signals, representing the read weighting vectors, into input lines of the memory, thereby retrieving data from the memory, generating write weighting vectors according to the write instructions, coupling write signals, representing the write weighting vectors, into output lines of the memory, thereby writing data into the memory.

Abstract: Embodiment of the invention are directed to transmitting signals between neurons of a hardware-implemented, spiking neural network (or SNN). The network includes neuronal connections, each including a synaptic unit connecting a pre-synaptic neuron to a post-synaptic neuron. Spikes received from the pre-synaptic neuron of said each neuronal connection are first modulated, in frequency, based on a synaptic weight stored on said each synaptic unit, to generate post-synaptic spikes, such that a first number of spikes received from the pre-synaptic neuron are translated into a second number of post-synaptic spikes. At least some of the spikes received from the pre-synaptic neuron may, each, be translated into a train of two or more post-synaptic spikes. The post-synaptic spikes generated are subsequently transmitted to the post-synaptic neuron of said each neuronal connection. The novel approach makes it possible to obtain a higher dynamic range in the synapse output.

Abstract: In a hardware-implemented approach for operating a neural network system, a neural network system is provided comprising a controller, a memory, and an interface connecting the controller to the memory, where the controller comprises a processing unit configured to execute a neural network and the memory comprises a neuromorphic memory device with a crossbar array structure that includes input lines and output lines interconnected at junctions via electronic devices. The electronic devices of the neuromorphic memory device are programmed to incrementally change states by coupling write signals into the input lines based on: write instructions received from the controller and write vectors generated by the interface. Data is retrieved from the neuromorphic memory device, according to a multiply-accumulate operation, by coupling read signals into one or more of the input lines of the neuromorphic memory device based on: read instructions from the controller and read vectors generated by the interface.

Abstract: The present disclosure relates to an apparatus that includes a neuromorphic spike integrator apparatus for neural networks. The apparatus receives at least one input signal encoding information in arrival time of the input signal at the apparatus. The received signal is weighted with a weight value corresponding to the arrival time. The weighted received signal is integrated into a current value of a state of the apparatus and a signal is output based on the current value of the state.

Abstract: The present disclosure relates to a neuromorphic neuron apparatus comprising an output generation block and at least one adaptation block. The apparatus has a current adaptation state variable corresponding to previously generated one or more signals. The output generation block is configured to use an activation function for generating a current output value based on the current adaptation state variable. The adaptation block is configured to repeatedly: compute an adaptation value of its current adaptation state variable using the current output value and a correction function; use the adaption value to update the current adaptation state variable to obtain an updated adaptation state variable, the updated adaptation state variable becoming the current adaptation state variable; receive a current signal; and cause the output generation block to generate a current output value based on the current adaptation state variable and input value that obtained from the received signal.

Abstract: Embodiment of the invention are directed to transmitting signals between neurons of a hardware-implemented, spiking neural network (or SNN). The network includes neuronal connections, each including a synaptic unit connecting a pre-synaptic neuron to a post-synaptic neuron. Spikes received from the pre-synaptic neuron of said each neuronal connection are first modulated, in frequency, based on a synaptic weight stored on said each synaptic unit, to generate post-synaptic spikes, such that a first number of spikes received from the pre-synaptic neuron are translated into a second number of post-synaptic spikes. At least some of the spikes received from the pre-synaptic neuron may, each, be translated into a train of two or more post-synaptic spikes. The post-synaptic spikes generated are subsequently transmitted to the post-synaptic neuron of said each neuronal connection. The novel approach makes it possible to obtain a higher dynamic range in the synapse output.

Abstract: Embodiments relate to a neuromorphic architecture for unsupervised feature learning using memristive synapses realized using phase-change devices. A spiking neural network architecture for unsupervised pattern learning and a spike-based learning algorithm compatible with phase-change synapses is described, and a feature-learning algorithm capable of performing a sequence of set operations on input patterns is provided. A learning rule for the extraction of certain features of the input that is compatible with spiking neurons and synapses with spike-based plasticity is also provided. The system enables enhanced pattern- and feature-extraction capabilities in neuromorphic systems.

Abstract: Embodiments relate to a neuromorphic architecture for unsupervised feature learning using memristive synapses realized using phase-change devices. A spiking neural network architecture for unsupervised pattern learning and a spike-based learning algorithm compatible with phase-change synapses is described, and a feature-learning algorithm capable of performing a sequence of set operations on input patterns is provided. A learning rule for the extraction of certain features of the input that is compatible with spiking neurons and synapses with spike-based plasticity is also provided. The system enables enhanced pattern- and feature-extraction capabilities in neuromorphic systems.

Abstract: A method for creating a global simulation model of an architecture for models of integrated circuits under development, including reading an architecture description file of the global model and storing information related to all of the possible configurations instantiating the components and storing the corresponding information, topologically connecting the interface signals, physically connecting the interface signals, at the level of each instance of the components using a component and connection rule table, and storing the corresponding information, and automatically generating the HDL-type and HLL-type source files of the global simulation model.

Abstract: The invention relates to a method for automatic recognition of simulation configurations of integrated circuits under design comprising at least two components connected to one another directly or indirectly, for the functional verification of the integrated circuits through simulation tests. The method includes a step for the acquisition of a simulation configuration by a server manager, a step for the sending of a request by a client manager to the server manager, a step for sending a response by the server manager to the client manager, and a step for the comparison by the client manager of the response with the requirements of the test, followed by a step for the disabling, activation and/or modification of certain parts of the test by the client manager in order to adapt the test to the configuration or signaling an error if the test cannot be adapted to the configuration.

Abstract: The present invention relates to a method and a system for generating a global simulation model of an architecture.