Patents by Inventor Andy BREWSTER

Andy BREWSTER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data transmission
    Patent number: 12511212
    Abstract: A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: December 30, 2025
    Assignee: Cirrus Logic Inc.
    Inventors: Neil Whyte, Andy Brewster, Jens Puchert
  • DATA TRANSMISSION
    Publication number: 20230056019
    Abstract: A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.
    Type: Application
    Filed: November 7, 2022
    Publication date: February 23, 2023
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Neil WHYTE, Andy BREWSTER, Jens PUCHERT
  • Data transmission
    Patent number: 11567848
    Abstract: A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 31, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Neil Whyte, Andy Brewster, Jens Puchert
  • Timing signal synchronisation
    Patent number: 11455002
    Abstract: A device comprising: a data interface comprising: a data input for receiving a data signal; a clock input for receiving a clock signal for clocking the data signal; and a timing input for receiving a first timing signal having a first frequency; and a timing signal generator configured to generate, based on the first timing signal and the data signal, a second timing signal having a second frequency, the first frequency being a integer multiple of the second frequency, a phase of the second timing signal being aligned with an event in the data signal.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: September 27, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Neil Whyte, Andy Brewster, Angus Black
  • DATA TRANSMISSION
    Publication number: 20220171691
    Abstract: A device, comprising: a main module; a plurality of secondary modules; and a data bus configured to enable data transmission between the main module and the plurality of secondary modules over a data line of the data bus; wherein each of the plurality of secondary modules is configured with a unique secondary address used by the main module to communicate with the respective secondary module over the data line, wherein the main module is operable to configure a first two or more of the plurality of secondary modules with a first common secondary address for simultaneous data transmission from the main module to the first two or more of the plurality of secondary modules over the data line.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 2, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Neil WHYTE, Andy BREWSTER, Jens PUCHERT