Patents by Inventor Andy C. Negoi

Andy C. Negoi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8154834
    Abstract: The present invention relates to a protection circuit and method of protecting a semiconductor circuit against a temporary excessive voltage on a supply line, wherein a first trigger signal is generated in response to a detection of an excessive voltage on the supply line and a clamp element (M1) is activated by applying a boosted second trigger signal at a voltage higher than the first trigger signal to a control terminal of the clamp element (M1) in response to said first trigger signal, to thereby generate a low resistive path between said supply line and a lower reference potential. Thereby, the clamp element (M1) is activated with a higher voltage and can thus be made smaller in width. Because the clamp element is smaller, a remote trigger circuit can be sized tighter and faster.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: April 10, 2012
    Assignee: NXP B.V.
    Inventor: Andy C. Negoi
  • Patent number: 8106705
    Abstract: The electronic circuit comprises a functional module (10), a condition signaling module (20), a reference module (30) and a control circuit (40). The condition signaling module (20) generates an indication signal (Imeas) indicative for PVT conditions local to the functional module. The PVT conditions comprise a set of conditions relevant for a module comprising at least one of a voltage supplied to said module, a temperature within an area occupied by said module and the process conditions relevant for said area The reference module (30) generates a reference signal (Iref) having a value that is substantially independent of said PVT-conditions. The control circuit (40) compares the indication signal (Imeas) and the reference signal (Iref), and for generating a control signal (pvt<1>, . . . , pvt<n>) for the functional module.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: January 31, 2012
    Assignee: Synopsys, Inc.
    Inventor: Andy C. Negoi
  • Patent number: 8026556
    Abstract: A method of manufacturing a resistive divider circuit, includes providing a silicon body having a plurality of opposing pairs of intermediate taps extending therefrom. Each tap comprises a thin silicon stem supporting a relatively wider silicon platform. A silicidation protection (SIPROT) layer is deposited over the body and intermediate taps and then patterned to expose the platform. A silicidation process is performed to silicidate the platform to form a contact pad of relatively low resistivity.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: September 27, 2011
    Assignee: NXP B.V.
    Inventor: Andy C. Negoi
  • Publication number: 20100027175
    Abstract: The present invention relates to a protection circuit and method of protecting a semiconductor circuit against a temporary excessive voltage on a supply line, wherein a first trigger signal is generated in response to a detection of an excessive voltage on the supply line and a clamp element (M1) is activated by applying a boosted second trigger signal at a voltage higher than the first trigger signal to a control terminal of the clamp element (M1) in response to said first trigger signal, to thereby generate a low resistive path between said supply line and a lower reference potential. Thereby, the clamp element (M1) is activated with a higher voltage and can thus be made smaller in width. Because the clamp element is smaller, a remote trigger circuit can be sized tighter and faster.
    Type: Application
    Filed: November 14, 2007
    Publication date: February 4, 2010
    Applicant: NXP, B.V.
    Inventor: Andy C. Negoi
  • Publication number: 20090174033
    Abstract: A method of manufacturing a resistive divider circuit, comprising providing a silicon body (6) having a plurality of opposing pairs of intermediate taps extending therefrom. Each tap comprises a thin silicon stem (61) supporting a relatively wider silicon platform (62). A silicidation protection (SIPROT) layer (S) is deposited over the body (6) and intermediate taps and then patterned to expose the platform (62). A silicidation process is performed to silicidate the platform to form a contact pad of relatively low resistivity.
    Type: Application
    Filed: April 19, 2007
    Publication date: July 9, 2009
    Applicant: NXP B.V.
    Inventor: Andy C. Negoi
  • Publication number: 20080100233
    Abstract: Apparatus comprising a charge pump (20) with multiple independently regulated outputs (V1, V2) for providing different voltage levels at each of said outputs. The charge pump (20) comprises a low voltage input (12), on/off regulation (30), and at least two charge stages (11, 21) which arc arranged in a cascaded manner. Each charge stage (11, 21) comprises a stage capacitor (16, 26), a switch (S1, S3), and a buffer (15, 25) for pumping a bottom plate of the stage capacitor (16, 26).
    Type: Application
    Filed: July 26, 2004
    Publication date: May 1, 2008
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Andy C. Negoi
  • Patent number: 7257009
    Abstract: The invention regards an improved voltage converter with increased current capability. The voltage converter architecture may be configured by software. In the prior art programmable charge pumps have been configured in such a way, that the unused stages were simply short circuited by a decoding logic. According to the invention these stages are used to increase the current capability of the first pumping stage. In particular the result is an increase in current capability of a proposed charge pump device by 10% to 15% without the need of additional parts and within the same area.
    Type: Grant
    Filed: April 14, 2002
    Date of Patent: August 14, 2007
    Assignee: NXP B.V.
    Inventor: Andy C. Negoi