Patents by Inventor Andy Chi-Hung Wei

Andy Chi-Hung Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods, apparatus and system for a passthrough-based architecture
    Patent number: 10559503
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: February 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
  • Method, apparatus and system for a high density middle of line flow
    Patent number: 10236350
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason Eugene Stephens, Vikrant Kumar Chauhan, David Michael Permana
  • METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE
    Publication number: 20180033701
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 1, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
  • Methods, apparatus and system for a passthrough-based architecture
    Patent number: 9818651
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 14, 2017
    Assignee: GlobalFoundries Inc.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
  • METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE
    Publication number: 20170263506
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.
    Type: Application
    Filed: March 11, 2016
    Publication date: September 14, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
  • METHOD, APPARATUS AND SYSTEM FOR A HIGH DENSITY MIDDLE OF LINE FLOW
    Publication number: 20170263715
    Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.
    Type: Application
    Filed: March 11, 2016
    Publication date: September 14, 2017
    Inventors: Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason Eugene Stephens, Vikrant Kumar Chauhan, David Michael Permana
  • SEMICONDUCTOR STRUCTURE WITH IMPROVED ISOLATION AND METHOD OF FABRICATION TO ENABLE FINE PITCH TRANSISTOR ARRAYS
    Publication number: 20150001628
    Abstract: An improved structure and method for forming isolation between two adjacent field effect transistors is disclosed. A large substrate cavity is formed between gates of the two adjacent transistors. The substrate cavity is filled with an epitaxial material such as epitaxial silicon, silicon germanium, or III-V compound semiconductor to form an epitaxial region. A cavity is then formed in the epitaxial material, dividing the epitaxial region into two epitaxial regions that serve as source-drain regions.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: Nicholas V. LiCausi, Daniel Pham, Andy Chi-Hung Wei, Zhenyu Hu